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DAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTL

DAC0_R8DH

DAC1_R12DH

DAC1_L12DH

DAC1_R8DH

DACC_R12DH

DACC_L12DH

DACC_R8DH

DAC0_DO

DAC1_DO

SWT

DAC0_R12DH

DAC0_L12DH


CTL

control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEN0 DBOFF0 DTEN0 DTSEL0 DWM0 DWBW0 DDMAEN0 DEN1 DBOFF1 DTEN1 DTSEL1 DWM1 DWBW1 DDMAEN1

DEN0 : DAC0 enable
bits : 0 - 0 (1 bit)

DBOFF0 : DAC0 output buffer turn off
bits : 1 - 1 (1 bit)

DTEN0 : DAC0 trigger enable
bits : 2 - 2 (1 bit)

DTSEL0 : DAC0 trigger selection
bits : 3 - 5 (3 bit)

DWM0 : DAC0 noise wave mode
bits : 6 - 7 (2 bit)

DWBW0 : DAC0 noise wave bit width
bits : 8 - 11 (4 bit)

DDMAEN0 : DAC0 DMA enable
bits : 12 - 12 (1 bit)

DEN1 : DAC1 enable
bits : 16 - 16 (1 bit)

DBOFF1 : DAC1 output buffer turn off
bits : 17 - 17 (1 bit)

DTEN1 : DAC1 trigger enable
bits : 18 - 18 (1 bit)

DTSEL1 : DAC1 trigger selection
bits : 19 - 21 (3 bit)

DWM1 : DAC1 noise wave mode
bits : 22 - 23 (2 bit)

DWBW1 : DAC1 noise wave bit width
bits : 24 - 27 (4 bit)

DDMAEN1 : DAC1 DMA enable
bits : 28 - 28 (1 bit)


DAC0_R8DH

DAC0 8-bit right aligned data holding register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC0_R8DH DAC0_R8DH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC0_DH

DAC0_DH : DAC0 8-bit right-aligned data
bits : 0 - 7 (8 bit)


DAC1_R12DH

DAC1 12-bit right-aligned data holding register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC1_R12DH DAC1_R12DH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC1_DH

DAC1_DH : DAC1 12-bit right-aligned data
bits : 0 - 11 (12 bit)


DAC1_L12DH

DAC1 12-bit left aligned data holding register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC1_L12DH DAC1_L12DH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC1_DH

DAC1_DH : DAC1 12-bit left-aligned data
bits : 4 - 15 (12 bit)


DAC1_R8DH

DAC1 8-bit right aligned data holding register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC1_R8DH DAC1_R8DH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC1_DH

DAC1_DH : DAC1 8-bit right-aligned data
bits : 0 - 7 (8 bit)


DACC_R12DH

DAC concurrent mode 12-bit right-aligned data holding register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DACC_R12DH DACC_R12DH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC0_DH DAC1_DH

DAC0_DH : DAC0 12-bit right-aligned data
bits : 0 - 11 (12 bit)

DAC1_DH : DAC1 12-bit right-aligned data
bits : 16 - 27 (12 bit)


DACC_L12DH

DAC concurrent mode 12-bit left aligned data holding register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DACC_L12DH DACC_L12DH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC0_DH DAC1_DH

DAC0_DH : DAC0 12-bit left-aligned data
bits : 4 - 15 (12 bit)

DAC1_DH : DAC1 12-bit left-aligned data
bits : 20 - 31 (12 bit)


DACC_R8DH

DAC concurrent mode 8-bit right aligned data holding register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DACC_R8DH DACC_R8DH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC0_DH DAC1_DH

DAC0_DH : DAC0 8-bit right-aligned data
bits : 0 - 7 (8 bit)

DAC1_DH : DAC1 8-bit right-aligned data
bits : 8 - 15 (8 bit)


DAC0_DO

DAC0 data output register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DAC0_DO DAC0_DO read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC0_DO

DAC0_DO : DAC0 data output
bits : 0 - 11 (12 bit)


DAC1_DO

DAC1 data output register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DAC1_DO DAC1_DO read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC1_DO

DAC1_DO : DAC1 data output
bits : 0 - 11 (12 bit)


SWT

software trigger register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWT SWT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWTR0 SWTR1

SWTR0 : DAC0 software trigger
bits : 0 - 0 (1 bit)

SWTR1 : DAC1 software trigger
bits : 1 - 1 (1 bit)


DAC0_R12DH

DAC0 12-bit right-aligned data holding register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC0_R12DH DAC0_R12DH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC0_DH

DAC0_DH : DAC0 12-bit right-aligned data
bits : 0 - 11 (12 bit)


DAC0_L12DH

DAC0 12-bit left-aligned data holding register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC0_L12DH DAC0_L12DH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC0_DH

DAC0_DH : DAC0 12-bit left-aligned data
bits : 4 - 15 (12 bit)



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