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DMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

INTF

CH0PADDR

CH0MADDR

CH1CTL

CH1CNT

CH1PADDR

CH1MADDR

CH2CTL

CH2CNT

CH2PADDR

CH2MADDR

INTC

CH3CTL

CH3CNT

CH3PADDR

CH3MADDR

CH4CTL

CH4CNT

CH4PADDR

CH4MADDR

CH0CTL

CH0CNT


INTF

Interrupt flag register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTF INTF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GIF0 FTFIF0 HTFIF0 ERRIF0 GIF1 FTFIF1 HTFIF1 ERRIF1 GIF2 FTFIF2 HTFIF2 ERRIF2 GIF3 FTFIF3 HTFIF3 ERRIF3 GIF4 FTFIF4 HTFIF4 ERRIF4 GIF5 FTFIF5 HTFIF5 ERRIF5 GIF6 FTFIF6 HTFIF6 ERRIF6

GIF0 : Global interrupt flag of channel 0
bits : 0 - 0 (1 bit)

FTFIF0 : Full Transfer finish flag of channe 0
bits : 1 - 1 (1 bit)

HTFIF0 : Half transfer finish flag of channel 0
bits : 2 - 2 (1 bit)

ERRIF0 : Error flag of channel 0
bits : 3 - 3 (1 bit)

GIF1 : Global interrupt flag of channel 1
bits : 4 - 4 (1 bit)

FTFIF1 : Full Transfer finish flag of channe 1
bits : 5 - 5 (1 bit)

HTFIF1 : Half transfer finish flag of channel 1
bits : 6 - 6 (1 bit)

ERRIF1 : Error flag of channel 1
bits : 7 - 7 (1 bit)

GIF2 : Global interrupt flag of channel 2
bits : 8 - 8 (1 bit)

FTFIF2 : Full Transfer finish flag of channe 2
bits : 9 - 9 (1 bit)

HTFIF2 : Half transfer finish flag of channel 2
bits : 10 - 10 (1 bit)

ERRIF2 : Error flag of channel 2
bits : 11 - 11 (1 bit)

GIF3 : Global interrupt flag of channel 3
bits : 12 - 12 (1 bit)

FTFIF3 : Full Transfer finish flag of channe 3
bits : 13 - 13 (1 bit)

HTFIF3 : Half transfer finish flag of channel 3
bits : 14 - 14 (1 bit)

ERRIF3 : Error flag of channel 3
bits : 15 - 15 (1 bit)

GIF4 : Global interrupt flag of channel 4
bits : 16 - 16 (1 bit)

FTFIF4 : Full Transfer finish flag of channe 4
bits : 17 - 17 (1 bit)

HTFIF4 : Half transfer finish flag of channel 4
bits : 18 - 18 (1 bit)

ERRIF4 : Error flag of channel 4
bits : 19 - 19 (1 bit)

GIF5 : Global interrupt flag of channel 5
bits : 20 - 20 (1 bit)

FTFIF5 : Full Transfer finish flag of channe 5
bits : 21 - 21 (1 bit)

HTFIF5 : Half transfer finish flag of channel 5
bits : 22 - 22 (1 bit)

ERRIF5 : Error flag of channel 5
bits : 23 - 23 (1 bit)

GIF6 : Global interrupt flag of channel 6
bits : 24 - 24 (1 bit)

FTFIF6 : Full Transfer finish flag of channe 6
bits : 25 - 25 (1 bit)

HTFIF6 : Half transfer finish flag of channel 6
bits : 26 - 26 (1 bit)

ERRIF6 : Error flag of channel 6
bits : 27 - 27 (1 bit)


CH0PADDR

Channel 0 peripheral base address register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0PADDR CH0PADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR

PADDR : Peripheral base address
bits : 0 - 31 (32 bit)


CH0MADDR

Channel 0 memory base address register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0MADDR CH0MADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory base address
bits : 0 - 31 (32 bit)


CH1CTL

Channel 1 control register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CTL CH1CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN FTFIE HTFIE ERRIE DIR CMEN PNAGA MNAGA PWIDTH MWIDTH PRIO M2M

CHEN : Channel enable
bits : 0 - 0 (1 bit)

FTFIE : Enable bit for channel full transfer finish interrupt
bits : 1 - 1 (1 bit)

HTFIE : Enable bit for channel half transfer finish interrupt
bits : 2 - 2 (1 bit)

ERRIE : Enable bit for channel error interrupt
bits : 3 - 3 (1 bit)

DIR : Transfer direction
bits : 4 - 4 (1 bit)

CMEN : Circular mode enable
bits : 5 - 5 (1 bit)

PNAGA : Next address generation algorithm of peripheral
bits : 6 - 6 (1 bit)

MNAGA : Next address generation algorithm of memory
bits : 7 - 7 (1 bit)

PWIDTH : Transfer data size of peripheral
bits : 8 - 9 (2 bit)

MWIDTH : Transfer data size of memory
bits : 10 - 11 (2 bit)

PRIO : Priority level
bits : 12 - 13 (2 bit)

M2M : Memory to Memory Mode
bits : 14 - 14 (1 bit)


CH1CNT

Channel 1 counter register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CNT CH1CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Transfer counter
bits : 0 - 15 (16 bit)


CH1PADDR

Channel 1 peripheral base address register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1PADDR CH1PADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR

PADDR : Peripheral base address
bits : 0 - 31 (32 bit)


CH1MADDR

Channel 1 memory base address register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1MADDR CH1MADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory base address
bits : 0 - 31 (32 bit)


CH2CTL

Channel 2 control register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2CTL CH2CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN FTFIE HTFIE ERRIE DIR CMEN PNAGA MNAGA PWIDTH MWIDTH PRIO M2M

CHEN : Channel enable
bits : 0 - 0 (1 bit)

FTFIE : Enable bit for channel full transfer finish interrupt
bits : 1 - 1 (1 bit)

HTFIE : Enable bit for channel half transfer finish interrupt
bits : 2 - 2 (1 bit)

ERRIE : Enable bit for channel error interrupt
bits : 3 - 3 (1 bit)

DIR : Transfer direction
bits : 4 - 4 (1 bit)

CMEN : Circular mode enable
bits : 5 - 5 (1 bit)

PNAGA : Next address generation algorithm of peripheral
bits : 6 - 6 (1 bit)

MNAGA : Next address generation algorithm of memory
bits : 7 - 7 (1 bit)

PWIDTH : Transfer data size of peripheral
bits : 8 - 9 (2 bit)

MWIDTH : Transfer data size of memory
bits : 10 - 11 (2 bit)

PRIO : Priority level
bits : 12 - 13 (2 bit)

M2M : Memory to Memory Mode
bits : 14 - 14 (1 bit)


CH2CNT

Channel 2 counter register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2CNT CH2CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Transfer counter
bits : 0 - 15 (16 bit)


CH2PADDR

Channel 2 peripheral base address register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2PADDR CH2PADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR

PADDR : Peripheral base address
bits : 0 - 31 (32 bit)


CH2MADDR

Channel 2 memory base address register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2MADDR CH2MADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory base address
bits : 0 - 31 (32 bit)


INTC

Interrupt flag clear register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INTC INTC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GIFC0 FTFIFC0 HTFIFC0 ERRIFC0 GIFC1 FTFIFC1 HTFIFC1 ERRIFC1 GIFC2 FTFIFC2 HTFIFC2 ERRIFC2 GIFC3 FTFIFC3 HTFIFC3 ERRIFC3 GIFC4 FTFIFC4 HTFIFC4 ERRIFC4 GIFC5 FTFIFC5 HTFIFC5 ERRIFC5 GIFC6 FTFIFC6 HTFIFC6 ERRIFC6

GIFC0 : Clear global interrupt flag of channel 0
bits : 0 - 0 (1 bit)

FTFIFC0 : Clear bit for full transfer finish flag of channel 0
bits : 1 - 1 (1 bit)

HTFIFC0 : Clear bit for half transfer finish flag of channel 0
bits : 2 - 2 (1 bit)

ERRIFC0 : Clear bit for error flag of channel 0
bits : 3 - 3 (1 bit)

GIFC1 : Clear global interrupt flag of channel 1
bits : 4 - 4 (1 bit)

FTFIFC1 : Clear bit for full transfer finish flag of channel 1
bits : 5 - 5 (1 bit)

HTFIFC1 : Clear bit for half transfer finish flag of channel 1
bits : 6 - 6 (1 bit)

ERRIFC1 : Clear bit for error flag of channel 1
bits : 7 - 7 (1 bit)

GIFC2 : Clear global interrupt flag of channel 2
bits : 8 - 8 (1 bit)

FTFIFC2 : Clear bit for full transfer finish flag of channel 2
bits : 9 - 9 (1 bit)

HTFIFC2 : Clear bit for half transfer finish flag of channel 2
bits : 10 - 10 (1 bit)

ERRIFC2 : Clear bit for error flag of channel 2
bits : 11 - 11 (1 bit)

GIFC3 : Clear global interrupt flag of channel 3
bits : 12 - 12 (1 bit)

FTFIFC3 : Clear bit for full transfer finish flag of channel 3
bits : 13 - 13 (1 bit)

HTFIFC3 : Clear bit for half transfer finish flag of channel 3
bits : 14 - 14 (1 bit)

ERRIFC3 : Clear bit for error flag of channel 3
bits : 15 - 15 (1 bit)

GIFC4 : Clear global interrupt flag of channel 4
bits : 16 - 16 (1 bit)

FTFIFC4 : Clear bit for full transfer finish flag of channel 4
bits : 17 - 17 (1 bit)

HTFIFC4 : Clear bit for half transfer finish flag of channel 4
bits : 18 - 18 (1 bit)

ERRIFC4 : Clear bit for error flag of channel 4
bits : 19 - 19 (1 bit)

GIFC5 : Clear global interrupt flag of channel 5
bits : 20 - 20 (1 bit)

FTFIFC5 : Clear bit for full transfer finish flag of channel 5
bits : 21 - 21 (1 bit)

HTFIFC5 : Clear bit for half transfer finish flag of channel 5
bits : 22 - 22 (1 bit)

ERRIFC5 : Clear bit for error flag of channel 5
bits : 23 - 23 (1 bit)

GIFC6 : Clear global interrupt flag of channel 6
bits : 24 - 24 (1 bit)

FTFIFC6 : Clear bit for full transfer finish flag of channel 6
bits : 25 - 25 (1 bit)

HTFIFC6 : Clear bit for half transfer finish flag of channel 6
bits : 26 - 26 (1 bit)

ERRIFC6 : Clear bit for error flag of channel 6
bits : 27 - 27 (1 bit)


CH3CTL

Channel 3 control register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3CTL CH3CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN FTFIE HTFIE ERRIE DIR CMEN PNAGA MNAGA PWIDTH MWIDTH PRIO M2M

CHEN : Channel enable
bits : 0 - 0 (1 bit)

FTFIE : Enable bit for channel full transfer finish interrupt
bits : 1 - 1 (1 bit)

HTFIE : Enable bit for channel half transfer finish interrupt
bits : 2 - 2 (1 bit)

ERRIE : Enable bit for channel error interrupt
bits : 3 - 3 (1 bit)

DIR : Transfer direction
bits : 4 - 4 (1 bit)

CMEN : Circular mode enable
bits : 5 - 5 (1 bit)

PNAGA : Next address generation algorithm of peripheral
bits : 6 - 6 (1 bit)

MNAGA : Next address generation algorithm of memory
bits : 7 - 7 (1 bit)

PWIDTH : Transfer data size of peripheral
bits : 8 - 9 (2 bit)

MWIDTH : Transfer data size of memory
bits : 10 - 11 (2 bit)

PRIO : Priority level
bits : 12 - 13 (2 bit)

M2M : Memory to Memory Mode
bits : 14 - 14 (1 bit)


CH3CNT

Channel 3 counter register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3CNT CH3CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Transfer counter
bits : 0 - 15 (16 bit)


CH3PADDR

Channel 3 peripheral base address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3PADDR CH3PADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR

PADDR : Peripheral base address
bits : 0 - 31 (32 bit)


CH3MADDR

Channel 3 memory base address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3MADDR CH3MADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory base address
bits : 0 - 31 (32 bit)


CH4CTL

Channel 4 control register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4CTL CH4CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN FTFIE HTFIE ERRIE DIR CMEN PNAGA MNAGA PWIDTH MWIDTH PRIO M2M

CHEN : Channel enable
bits : 0 - 0 (1 bit)

FTFIE : Enable bit for channel full transfer finish interrupt
bits : 1 - 1 (1 bit)

HTFIE : Enable bit for channel half transfer finish interrupt
bits : 2 - 2 (1 bit)

ERRIE : Enable bit for channel error interrupt
bits : 3 - 3 (1 bit)

DIR : Transfer direction
bits : 4 - 4 (1 bit)

CMEN : Circular mode enable
bits : 5 - 5 (1 bit)

PNAGA : Next address generation algorithm of peripheral
bits : 6 - 6 (1 bit)

MNAGA : Next address generation algorithm of memory
bits : 7 - 7 (1 bit)

PWIDTH : Transfer data size of peripheral
bits : 8 - 9 (2 bit)

MWIDTH : Transfer data size of memory
bits : 10 - 11 (2 bit)

PRIO : Priority level
bits : 12 - 13 (2 bit)

M2M : Memory to Memory Mode
bits : 14 - 14 (1 bit)


CH4CNT

Channel 4 counter register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4CNT CH4CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Transfer counter
bits : 0 - 15 (16 bit)


CH4PADDR

Channel 4 peripheral base address register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4PADDR CH4PADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR

PADDR : Peripheral base address
bits : 0 - 31 (32 bit)


CH4MADDR

Channel 4 memory base address register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4MADDR CH4MADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory base address
bits : 0 - 31 (32 bit)


CH0CTL

Channel 0 control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0CTL CH0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN FTFIE HTFIE ERRIE DIR CMEN PNAGA MNAGA PWIDTH MWIDTH PRIO M2M

CHEN : Channel enable
bits : 0 - 0 (1 bit)

FTFIE : Enable bit for channel full transfer finish interrupt
bits : 1 - 1 (1 bit)

HTFIE : Enable bit for channel half transfer finish interrupt
bits : 2 - 2 (1 bit)

ERRIE : Enable bit for channel error interrupt
bits : 3 - 3 (1 bit)

DIR : Transfer direction
bits : 4 - 4 (1 bit)

CMEN : Circular mode enable
bits : 5 - 5 (1 bit)

PNAGA : Next address generation algorithm of peripheral
bits : 6 - 6 (1 bit)

MNAGA : Next address generation algorithm of memory
bits : 7 - 7 (1 bit)

PWIDTH : Transfer data size of peripheral
bits : 8 - 9 (2 bit)

MWIDTH : Transfer data size of memory
bits : 10 - 11 (2 bit)

PRIO : Priority level
bits : 12 - 13 (2 bit)

M2M : Memory to Memory Mode
bits : 14 - 14 (1 bit)


CH0CNT

Channel 0 counter register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0CNT CH0CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Transfer counter
bits : 0 - 15 (16 bit)



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