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EXTI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

INTEN

SWIEV

PD

EVEN

RTEN

FTEN


INTEN

Interrupt enable register (EXTI_INTEN)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTEN0 INTEN1 INTEN2 INTEN3 INTEN4 INTEN5 INTEN6 INTEN7 INTEN8 INTEN9 INTEN10 INTEN11 INTEN12 INTEN13 INTEN14 INTEN15 INTEN16 INTEN17 INTEN18 INTEN19

INTEN0 : Enable Interrupt on line 0
bits : 0 - 0 (1 bit)

INTEN1 : Enable Interrupt on line 1
bits : 1 - 1 (1 bit)

INTEN2 : Enable Interrupt on line 2
bits : 2 - 2 (1 bit)

INTEN3 : Enable Interrupt on line 3
bits : 3 - 3 (1 bit)

INTEN4 : Enable Interrupt on line 4
bits : 4 - 4 (1 bit)

INTEN5 : Enable Interrupt on line 5
bits : 5 - 5 (1 bit)

INTEN6 : Enable Interrupt on line 6
bits : 6 - 6 (1 bit)

INTEN7 : Enable Interrupt on line 7
bits : 7 - 7 (1 bit)

INTEN8 : Enable Interrupt on line 8
bits : 8 - 8 (1 bit)

INTEN9 : Enable Interrupt on line 9
bits : 9 - 9 (1 bit)

INTEN10 : Enable Interrupt on line 10
bits : 10 - 10 (1 bit)

INTEN11 : Enable Interrupt on line 11
bits : 11 - 11 (1 bit)

INTEN12 : Enable Interrupt on line 12
bits : 12 - 12 (1 bit)

INTEN13 : Enable Interrupt on line 13
bits : 13 - 13 (1 bit)

INTEN14 : Enable Interrupt on line 14
bits : 14 - 14 (1 bit)

INTEN15 : Enable Interrupt on line 15
bits : 15 - 15 (1 bit)

INTEN16 : Enable Interrupt on line 16
bits : 16 - 16 (1 bit)

INTEN17 : Enable Interrupt on line 17
bits : 17 - 17 (1 bit)

INTEN18 : Enable Interrupt on line 18
bits : 18 - 18 (1 bit)

INTEN19 : Enable Interrupt on line 19
bits : 19 - 19 (1 bit)


SWIEV

Software interrupt event register (EXTI_SWIEV)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWIEV SWIEV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWIEV0 SWIEV1 SWIEV2 SWIEV3 SWIEV4 SWIEV5 SWIEV6 SWIEV7 SWIEV8 SWIEV9 SWIEV10 SWIEV11 SWIEV12 SWIEV13 SWIEV14 SWIEV15 SWIEV16 SWIEV17 SWIEV18 SWIEV19

SWIEV0 : Interrupt/Event software trigger on line 0
bits : 0 - 0 (1 bit)

SWIEV1 : Interrupt/Event software trigger on line 1
bits : 1 - 1 (1 bit)

SWIEV2 : Interrupt/Event software trigger on line 2
bits : 2 - 2 (1 bit)

SWIEV3 : Interrupt/Event software trigger on line 3
bits : 3 - 3 (1 bit)

SWIEV4 : Interrupt/Event software trigger on line 4
bits : 4 - 4 (1 bit)

SWIEV5 : Interrupt/Event software trigger on line 5
bits : 5 - 5 (1 bit)

SWIEV6 : Interrupt/Event software trigger on line 6
bits : 6 - 6 (1 bit)

SWIEV7 : Interrupt/Event software trigger on line 7
bits : 7 - 7 (1 bit)

SWIEV8 : Interrupt/Event software trigger on line 8
bits : 8 - 8 (1 bit)

SWIEV9 : Interrupt/Event software trigger on line 9
bits : 9 - 9 (1 bit)

SWIEV10 : Interrupt/Event software trigger on line 10
bits : 10 - 10 (1 bit)

SWIEV11 : Interrupt/Event software trigger on line 11
bits : 11 - 11 (1 bit)

SWIEV12 : Interrupt/Event software trigger on line 12
bits : 12 - 12 (1 bit)

SWIEV13 : Interrupt/Event software trigger on line 13
bits : 13 - 13 (1 bit)

SWIEV14 : Interrupt/Event software trigger on line 14
bits : 14 - 14 (1 bit)

SWIEV15 : Interrupt/Event software trigger on line 15
bits : 15 - 15 (1 bit)

SWIEV16 : Interrupt/Event software trigger on line 16
bits : 16 - 16 (1 bit)

SWIEV17 : Interrupt/Event software trigger on line 17
bits : 17 - 17 (1 bit)

SWIEV18 : Interrupt/Event software trigger on line 18
bits : 18 - 18 (1 bit)

SWIEV19 : Interrupt/Event software trigger on line 19
bits : 19 - 19 (1 bit)


PD

Pending register (EXTI_PD)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD PD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19

PD0 : Interrupt pending status of line 0
bits : 0 - 0 (1 bit)

PD1 : Interrupt pending status of line 1
bits : 1 - 1 (1 bit)

PD2 : Interrupt pending status of line 2
bits : 2 - 2 (1 bit)

PD3 : Interrupt pending status of line 3
bits : 3 - 3 (1 bit)

PD4 : Interrupt pending status of line 4
bits : 4 - 4 (1 bit)

PD5 : Interrupt pending status of line 5
bits : 5 - 5 (1 bit)

PD6 : Interrupt pending status of line 6
bits : 6 - 6 (1 bit)

PD7 : Interrupt pending status of line 7
bits : 7 - 7 (1 bit)

PD8 : Interrupt pending status of line 8
bits : 8 - 8 (1 bit)

PD9 : Interrupt pending status of line 9
bits : 9 - 9 (1 bit)

PD10 : Interrupt pending status of line 10
bits : 10 - 10 (1 bit)

PD11 : Interrupt pending status of line 11
bits : 11 - 11 (1 bit)

PD12 : Interrupt pending status of line 12
bits : 12 - 12 (1 bit)

PD13 : Interrupt pending status of line 13
bits : 13 - 13 (1 bit)

PD14 : Interrupt pending status of line 14
bits : 14 - 14 (1 bit)

PD15 : Interrupt pending status of line 15
bits : 15 - 15 (1 bit)

PD16 : Interrupt pending status of line 16
bits : 16 - 16 (1 bit)

PD17 : Interrupt pending status of line 17
bits : 17 - 17 (1 bit)

PD18 : Interrupt pending status of line 18
bits : 18 - 18 (1 bit)

PD19 : Interrupt pending status of line 19
bits : 19 - 19 (1 bit)


EVEN

Event enable register (EXTI_EVEN)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVEN EVEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVEN0 EVEN1 EVEN2 EVEN3 EVEN4 EVEN5 EVEN6 EVEN7 EVEN8 EVEN9 EVEN10 EVEN11 EVEN12 EVEN13 EVEN14 EVEN15 EVEN16 EVEN17 EVEN18 EVEN19

EVEN0 : Enable Event on line 0
bits : 0 - 0 (1 bit)

EVEN1 : Enable Event on line 1
bits : 1 - 1 (1 bit)

EVEN2 : Enable Event on line 2
bits : 2 - 2 (1 bit)

EVEN3 : Enable Event on line 3
bits : 3 - 3 (1 bit)

EVEN4 : Enable Event on line 4
bits : 4 - 4 (1 bit)

EVEN5 : Enable Event on line 5
bits : 5 - 5 (1 bit)

EVEN6 : Enable Event on line 6
bits : 6 - 6 (1 bit)

EVEN7 : Enable Event on line 7
bits : 7 - 7 (1 bit)

EVEN8 : Enable Event on line 8
bits : 8 - 8 (1 bit)

EVEN9 : Enable Event on line 9
bits : 9 - 9 (1 bit)

EVEN10 : Enable Event on line 10
bits : 10 - 10 (1 bit)

EVEN11 : Enable Event on line 11
bits : 11 - 11 (1 bit)

EVEN12 : Enable Event on line 12
bits : 12 - 12 (1 bit)

EVEN13 : Enable Event on line 13
bits : 13 - 13 (1 bit)

EVEN14 : Enable Event on line 14
bits : 14 - 14 (1 bit)

EVEN15 : Enable Event on line 15
bits : 15 - 15 (1 bit)

EVEN16 : Enable Event on line 16
bits : 16 - 16 (1 bit)

EVEN17 : Enable Event on line 17
bits : 17 - 17 (1 bit)

EVEN18 : Enable Event on line 18
bits : 18 - 18 (1 bit)

EVEN19 : Enable Event on line 19
bits : 19 - 19 (1 bit)


RTEN

Rising Edge Trigger Enable register (EXTI_RTEN)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTEN RTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTEN0 RTEN1 RTEN2 RTEN3 RTEN4 RTEN5 RTEN6 RTEN7 RTEN8 RTEN9 RTEN10 RTEN11 RTEN12 RTEN13 RTEN14 RTEN15 RTEN16 RTEN17 RTEN18 RTEN19

RTEN0 : Rising edge trigger enable of line 0
bits : 0 - 0 (1 bit)

RTEN1 : Rising edge trigger enable of line 1
bits : 1 - 1 (1 bit)

RTEN2 : Rising edge trigger enable of line 2
bits : 2 - 2 (1 bit)

RTEN3 : Rising edge trigger enable of line 3
bits : 3 - 3 (1 bit)

RTEN4 : Rising edge trigger enable of line 4
bits : 4 - 4 (1 bit)

RTEN5 : Rising edge trigger enable of line 5
bits : 5 - 5 (1 bit)

RTEN6 : Rising edge trigger enable of line 6
bits : 6 - 6 (1 bit)

RTEN7 : Rising edge trigger enable of line 7
bits : 7 - 7 (1 bit)

RTEN8 : Rising edge trigger enable of line 8
bits : 8 - 8 (1 bit)

RTEN9 : Rising edge trigger enable of line 9
bits : 9 - 9 (1 bit)

RTEN10 : Rising edge trigger enable of line 10
bits : 10 - 10 (1 bit)

RTEN11 : Rising edge trigger enable of line 11
bits : 11 - 11 (1 bit)

RTEN12 : Rising edge trigger enable of line 12
bits : 12 - 12 (1 bit)

RTEN13 : Rising edge trigger enable of line 13
bits : 13 - 13 (1 bit)

RTEN14 : Rising edge trigger enable of line 14
bits : 14 - 14 (1 bit)

RTEN15 : Rising edge trigger enable of line 15
bits : 15 - 15 (1 bit)

RTEN16 : Rising edge trigger enable of line 16
bits : 16 - 16 (1 bit)

RTEN17 : Rising edge trigger enable of line 17
bits : 17 - 17 (1 bit)

RTEN18 : Rising edge trigger enable of line 18
bits : 18 - 18 (1 bit)

RTEN19 : Rising edge trigger enable of line 19
bits : 19 - 19 (1 bit)


FTEN

Falling Egde Trigger Enable register (EXTI_FTEN)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FTEN FTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTEN0 FTEN1 FTEN2 FTEN3 FTEN4 FTEN5 FTEN6 FTEN7 FTEN8 FTEN9 FTEN10 FTEN11 FTEN12 FTEN13 FTEN14 FTEN15 FTEN16 FTEN17 FTEN18 FTEN19

FTEN0 : Falling edge trigger enable of line 0
bits : 0 - 0 (1 bit)

FTEN1 : Falling edge trigger enable of line 1
bits : 1 - 1 (1 bit)

FTEN2 : Falling edge trigger enable of line 2
bits : 2 - 2 (1 bit)

FTEN3 : Falling edge trigger enable of line 3
bits : 3 - 3 (1 bit)

FTEN4 : Falling edge trigger enable of line 4
bits : 4 - 4 (1 bit)

FTEN5 : Falling edge trigger enable of line 5
bits : 5 - 5 (1 bit)

FTEN6 : Falling edge trigger enable of line 6
bits : 6 - 6 (1 bit)

FTEN7 : Falling edge trigger enable of line 7
bits : 7 - 7 (1 bit)

FTEN8 : Falling edge trigger enable of line 8
bits : 8 - 8 (1 bit)

FTEN9 : Falling edge trigger enable of line 9
bits : 9 - 9 (1 bit)

FTEN10 : Falling edge trigger enable of line 10
bits : 10 - 10 (1 bit)

FTEN11 : Falling edge trigger enable of line 11
bits : 11 - 11 (1 bit)

FTEN12 : Falling edge trigger enable of line 12
bits : 12 - 12 (1 bit)

FTEN13 : Falling edge trigger enable of line 13
bits : 13 - 13 (1 bit)

FTEN14 : Falling edge trigger enable of line 14
bits : 14 - 14 (1 bit)

FTEN15 : Falling edge trigger enable of line 15
bits : 15 - 15 (1 bit)

FTEN16 : Falling edge trigger enable of line 16
bits : 16 - 16 (1 bit)

FTEN17 : Falling edge trigger enable of line 17
bits : 17 - 17 (1 bit)

FTEN18 : Falling edge trigger enable of line 18
bits : 18 - 18 (1 bit)

FTEN19 : Falling edge trigger enable of line 19
bits : 19 - 19 (1 bit)



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