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GPIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTL0

BOP

BC

LOCK

CTL1

ISTAT

OCTL


CTL0

port control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL0 CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD0 CTL0 MD1 CTL1 MD2 CTL2 MD3 CTL3 MD4 CTL4 MD5 CTL5 MD6 CTL6 MD7 CTL7

MD0 : Port x mode bits (x = 0)
bits : 0 - 1 (2 bit)

CTL0 : Port x configuration bits (x = 0)
bits : 2 - 3 (2 bit)

MD1 : Port x mode bits (x = 1)
bits : 4 - 5 (2 bit)

CTL1 : Port x configuration bits (x = 1)
bits : 6 - 7 (2 bit)

MD2 : Port x mode bits (x = 2 )
bits : 8 - 9 (2 bit)

CTL2 : Port x configuration bits (x = 2)
bits : 10 - 11 (2 bit)

MD3 : Port x mode bits (x = 3 )
bits : 12 - 13 (2 bit)

CTL3 : Port x configuration bits (x = 3)
bits : 14 - 15 (2 bit)

MD4 : Port x mode bits (x = 4)
bits : 16 - 17 (2 bit)

CTL4 : Port x configuration bits (x = 4)
bits : 18 - 19 (2 bit)

MD5 : Port x mode bits (x = 5)
bits : 20 - 21 (2 bit)

CTL5 : Port x configuration bits (x = 5)
bits : 22 - 23 (2 bit)

MD6 : Port x mode bits (x = 6)
bits : 24 - 25 (2 bit)

CTL6 : Port x configuration bits (x = 6)
bits : 26 - 27 (2 bit)

MD7 : Port x mode bits (x = 7)
bits : 28 - 29 (2 bit)

CTL7 : Port x configuration bits (x = 7)
bits : 30 - 31 (2 bit)


BOP

Port bit operate register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

BOP BOP write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOP0 BOP1 BOP2 BOP3 BOP4 BOP5 BOP6 BOP7 BOP8 BOP9 BOP10 BOP11 BOP12 BOP13 BOP14 BOP15 CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15

BOP0 : Port 0 Set bit
bits : 0 - 0 (1 bit)

BOP1 : Port 1 Set bit
bits : 1 - 1 (1 bit)

BOP2 : Port 2 Set bit
bits : 2 - 2 (1 bit)

BOP3 : Port 3 Set bit
bits : 3 - 3 (1 bit)

BOP4 : Port 4 Set bit
bits : 4 - 4 (1 bit)

BOP5 : Port 5 Set bit
bits : 5 - 5 (1 bit)

BOP6 : Port 6 Set bit
bits : 6 - 6 (1 bit)

BOP7 : Port 7 Set bit
bits : 7 - 7 (1 bit)

BOP8 : Port 8 Set bit
bits : 8 - 8 (1 bit)

BOP9 : Port 9 Set bit
bits : 9 - 9 (1 bit)

BOP10 : Port 10 Set bit
bits : 10 - 10 (1 bit)

BOP11 : Port 11 Set bit
bits : 11 - 11 (1 bit)

BOP12 : Port 12 Set bit
bits : 12 - 12 (1 bit)

BOP13 : Port 13 Set bit
bits : 13 - 13 (1 bit)

BOP14 : Port 14 Set bit
bits : 14 - 14 (1 bit)

BOP15 : Port 15 Set bit
bits : 15 - 15 (1 bit)

CR0 : Port 0 Clear bit
bits : 16 - 16 (1 bit)

CR1 : Port 1 Clear bit
bits : 17 - 17 (1 bit)

CR2 : Port 2 Clear bit
bits : 18 - 18 (1 bit)

CR3 : Port 3 Clear bit
bits : 19 - 19 (1 bit)

CR4 : Port 4 Clear bit
bits : 20 - 20 (1 bit)

CR5 : Port 5 Clear bit
bits : 21 - 21 (1 bit)

CR6 : Port 6 Clear bit
bits : 22 - 22 (1 bit)

CR7 : Port 7 Clear bit
bits : 23 - 23 (1 bit)

CR8 : Port 8 Clear bit
bits : 24 - 24 (1 bit)

CR9 : Port 9 Clear bit
bits : 25 - 25 (1 bit)

CR10 : Port 10 Clear bit
bits : 26 - 26 (1 bit)

CR11 : Port 11 Clear bit
bits : 27 - 27 (1 bit)

CR12 : Port 12 Clear bit
bits : 28 - 28 (1 bit)

CR13 : Port 13 Clear bit
bits : 29 - 29 (1 bit)

CR14 : Port 14 Clear bit
bits : 30 - 30 (1 bit)

CR15 : Port 15 Clear bit
bits : 31 - 31 (1 bit)


BC

Port bit clear register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

BC BC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15

CR0 : Port 0 Clear bit
bits : 0 - 0 (1 bit)

CR1 : Port 1 Clear bit
bits : 1 - 1 (1 bit)

CR2 : Port 2 Clear bit
bits : 2 - 2 (1 bit)

CR3 : Port 3 Clear bit
bits : 3 - 3 (1 bit)

CR4 : Port 4 Clear bit
bits : 4 - 4 (1 bit)

CR5 : Port 5 Clear bit
bits : 5 - 5 (1 bit)

CR6 : Port 6 Clear bit
bits : 6 - 6 (1 bit)

CR7 : Port 7 Clear bit
bits : 7 - 7 (1 bit)

CR8 : Port 8 Clear bit
bits : 8 - 8 (1 bit)

CR9 : Port 9 Clear bit
bits : 9 - 9 (1 bit)

CR10 : Port 10 Clear bit
bits : 10 - 10 (1 bit)

CR11 : Port 11 Clear bit
bits : 11 - 11 (1 bit)

CR12 : Port 12 Clear bit
bits : 12 - 12 (1 bit)

CR13 : Port 13 Clear bit
bits : 13 - 13 (1 bit)

CR14 : Port 14 Clear bit
bits : 14 - 14 (1 bit)

CR15 : Port 15 Clear bit
bits : 15 - 15 (1 bit)


LOCK

GPIO port configuration lock register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LK0 LK1 LK2 LK3 LK4 LK5 LK6 LK7 LK8 LK9 LK10 LK11 LK12 LK13 LK14 LK15 LKK

LK0 : Port Lock bit 0
bits : 0 - 0 (1 bit)

LK1 : Port Lock bit 1
bits : 1 - 1 (1 bit)

LK2 : Port Lock bit 2
bits : 2 - 2 (1 bit)

LK3 : Port Lock bit 3
bits : 3 - 3 (1 bit)

LK4 : Port Lock bit 4
bits : 4 - 4 (1 bit)

LK5 : Port Lock bit 5
bits : 5 - 5 (1 bit)

LK6 : Port Lock bit 6
bits : 6 - 6 (1 bit)

LK7 : Port Lock bit 7
bits : 7 - 7 (1 bit)

LK8 : Port Lock bit 8
bits : 8 - 8 (1 bit)

LK9 : Port Lock bit 9
bits : 9 - 9 (1 bit)

LK10 : Port Lock bit 10
bits : 10 - 10 (1 bit)

LK11 : Port Lock bit 11
bits : 11 - 11 (1 bit)

LK12 : Port Lock bit 12
bits : 12 - 12 (1 bit)

LK13 : Port Lock bit 13
bits : 13 - 13 (1 bit)

LK14 : Port Lock bit 14
bits : 14 - 14 (1 bit)

LK15 : Port Lock bit 15
bits : 15 - 15 (1 bit)

LKK : Lock sequence key
bits : 16 - 16 (1 bit)


CTL1

port control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL1 CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD8 CTL8 MD9 CTL9 MD10 CTL10 MD11 CTL11 MD12 CTL12 MD13 CTL13 MD14 CTL14 MD15 CTL15

MD8 : Port x mode bits (x = 8)
bits : 0 - 1 (2 bit)

CTL8 : Port x configuration bits (x = 8)
bits : 2 - 3 (2 bit)

MD9 : Port x mode bits (x = 9)
bits : 4 - 5 (2 bit)

CTL9 : Port x configuration bits (x = 9)
bits : 6 - 7 (2 bit)

MD10 : Port x mode bits (x = 10 )
bits : 8 - 9 (2 bit)

CTL10 : Port x configuration bits (x = 10)
bits : 10 - 11 (2 bit)

MD11 : Port x mode bits (x = 11 )
bits : 12 - 13 (2 bit)

CTL11 : Port x configuration bits (x = 11)
bits : 14 - 15 (2 bit)

MD12 : Port x mode bits (x = 12)
bits : 16 - 17 (2 bit)

CTL12 : Port x configuration bits (x = 12)
bits : 18 - 19 (2 bit)

MD13 : Port x mode bits (x = 13)
bits : 20 - 21 (2 bit)

CTL13 : Port x configuration bits (x = 13)
bits : 22 - 23 (2 bit)

MD14 : Port x mode bits (x = 14)
bits : 24 - 25 (2 bit)

CTL14 : Port x configuration bits (x = 14)
bits : 26 - 27 (2 bit)

MD15 : Port x mode bits (x = 15)
bits : 28 - 29 (2 bit)

CTL15 : Port x configuration bits (x = 15)
bits : 30 - 31 (2 bit)


ISTAT

Port input status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISTAT ISTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISTAT0 ISTAT1 ISTAT2 ISTAT3 ISTAT4 ISTAT5 ISTAT6 ISTAT7 ISTAT8 ISTAT9 ISTAT10 ISTAT11 ISTAT12 ISTAT13 ISTAT14 ISTAT15

ISTAT0 : Port input status
bits : 0 - 0 (1 bit)

ISTAT1 : Port input status
bits : 1 - 1 (1 bit)

ISTAT2 : Port input status
bits : 2 - 2 (1 bit)

ISTAT3 : Port input status
bits : 3 - 3 (1 bit)

ISTAT4 : Port input status
bits : 4 - 4 (1 bit)

ISTAT5 : Port input status
bits : 5 - 5 (1 bit)

ISTAT6 : Port input status
bits : 6 - 6 (1 bit)

ISTAT7 : Port input status
bits : 7 - 7 (1 bit)

ISTAT8 : Port input status
bits : 8 - 8 (1 bit)

ISTAT9 : Port input status
bits : 9 - 9 (1 bit)

ISTAT10 : Port input status
bits : 10 - 10 (1 bit)

ISTAT11 : Port input status
bits : 11 - 11 (1 bit)

ISTAT12 : Port input status
bits : 12 - 12 (1 bit)

ISTAT13 : Port input status
bits : 13 - 13 (1 bit)

ISTAT14 : Port input status
bits : 14 - 14 (1 bit)

ISTAT15 : Port input status
bits : 15 - 15 (1 bit)


OCTL

Port output control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCTL OCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCTL0 OCTL1 OCTL2 OCTL3 OCTL4 OCTL5 OCTL6 OCTL7 OCTL8 OCTL9 OCTL10 OCTL11 OCTL12 OCTL13 OCTL14 OCTL15

OCTL0 : Port output control
bits : 0 - 0 (1 bit)

OCTL1 : Port output control
bits : 1 - 1 (1 bit)

OCTL2 : Port output control
bits : 2 - 2 (1 bit)

OCTL3 : Port output control
bits : 3 - 3 (1 bit)

OCTL4 : Port output control
bits : 4 - 4 (1 bit)

OCTL5 : Port output control
bits : 5 - 5 (1 bit)

OCTL6 : Port output control
bits : 6 - 6 (1 bit)

OCTL7 : Port output control
bits : 7 - 7 (1 bit)

OCTL8 : Port output control
bits : 8 - 8 (1 bit)

OCTL9 : Port output control
bits : 9 - 9 (1 bit)

OCTL10 : Port output control
bits : 10 - 10 (1 bit)

OCTL11 : Port output control
bits : 11 - 11 (1 bit)

OCTL12 : Port output control
bits : 12 - 12 (1 bit)

OCTL13 : Port output control
bits : 13 - 13 (1 bit)

OCTL14 : Port output control
bits : 14 - 14 (1 bit)

OCTL15 : Port output control
bits : 15 - 15 (1 bit)



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