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PMU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTL

CS


CTL

power control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LDOLP STBMOD WURST STBRST LVDEN LVDT BKPWEN

LDOLP : LDO Low Power Mode
bits : 0 - 0 (1 bit)

STBMOD : Standby Mode
bits : 1 - 1 (1 bit)

WURST : Wakeup Flag Reset
bits : 2 - 2 (1 bit)

STBRST : Standby Flag Reset
bits : 3 - 3 (1 bit)

LVDEN : Low Voltage Detector Enable
bits : 4 - 4 (1 bit)

LVDT : Low Voltage Detector Threshold
bits : 5 - 7 (3 bit)

BKPWEN : Backup Domain Write Enable
bits : 8 - 8 (1 bit)


CS

power control/status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS CS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUF STBF LVDF WUPEN

WUF : Wakeup flag
bits : 0 - 0 (1 bit)
access : read-only

STBF : Standby flag
bits : 1 - 1 (1 bit)
access : read-only

LVDF : Low Voltage Detector Status Flag
bits : 2 - 2 (1 bit)
access : read-only

WUPEN : Enable WKUP pin
bits : 8 - 8 (1 bit)
access : read-write



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