PWRCTL

RSPCMDIDX

RESP0

RESP1

RESP2

RESP3

DATATO

DATALEN

DATACTL

DATACNT

STAT

INTC

INTEN

CLKCTL

FIFOCNT

CMDAGMT

FIFO

CMDCTL

PWRCTL : SDIO power control bits
bits : 0 - 1 (2 bit)

RSPCMDIDX : Last response command index
bits : 0 - 5 (6 bit)

RESP0 : Card state
bits : 0 - 31 (32 bit)

RESP1 : Card state
bits : 0 - 31 (32 bit)

RESP2 : Card state
bits : 0 - 31 (32 bit)

RESP3 : Response register 3
bits : 0 - 31 (32 bit)

DATATO : Data timeout period
bits : 0 - 31 (32 bit)

DATALEN : Data transfer length
bits : 0 - 24 (25 bit)

DATAEN : Data transfer enabled bit
bits : 0 - 0 (1 bit)

DATADIR : Data transfer direction
bits : 1 - 1 (1 bit)

TRANSMOD : Data transfer mode
bits : 2 - 2 (1 bit)

DMAEN : DMA enable bit
bits : 3 - 3 (1 bit)

BLKSZ : Data block size
bits : 4 - 7 (4 bit)

RWEN : Read wait mode enabled
bits : 8 - 8 (1 bit)

RWSTOP : Read wait stop
bits : 9 - 9 (1 bit)

RWTYPE : Read wait type
bits : 10 - 10 (1 bit)

IOEN : SD I/O specific function enable
bits : 11 - 11 (1 bit)

DATACNT : Data count value
bits : 0 - 24 (25 bit)

CCRCERR : Command response received
bits : 0 - 0 (1 bit)

DTCRCERR : Data block sent/received
bits : 1 - 1 (1 bit)

CMDTMOUT : Command response timeout
bits : 2 - 2 (1 bit)

DTTMOUT : Data timeout
bits : 3 - 3 (1 bit)

TXURE : Transmit FIFO underrun error occurs
bits : 4 - 4 (1 bit)

RXORE : Received FIFO overrun error occurs
bits : 5 - 5 (1 bit)

CMDRECV : Command response received
bits : 6 - 6 (1 bit)

CMDSEND : Command sent
bits : 7 - 7 (1 bit)

DTEND : Data end
bits : 8 - 8 (1 bit)

STBITE : Start bit error in the bus
bits : 9 - 9 (1 bit)

DTBLKEND : Data block sent/received
bits : 10 - 10 (1 bit)

CMDRUN : Command transmission in progress
bits : 11 - 11 (1 bit)

TXRUN : Data transmission in progress
bits : 12 - 12 (1 bit)

RXRUN : Data reception in progress
bits : 13 - 13 (1 bit)

TFH : Transmit FIFO is half empty
bits : 14 - 14 (1 bit)

RFH : Receive FIFO is half full
bits : 15 - 15 (1 bit)

TFF : Transmit FIFO is full
bits : 16 - 16 (1 bit)

RFF : Receive FIFO is full
bits : 17 - 17 (1 bit)

TFE : Transmit FIFO is empty
bits : 18 - 18 (1 bit)

RFE : Receive FIFO is empty
bits : 19 - 19 (1 bit)

TXDTVAL : Data is valid in transmit FIFO
bits : 20 - 20 (1 bit)

RXDTVAL : Data is valid in receive FIFO
bits : 21 - 21 (1 bit)

SDIOINT : SD I/O interrupt received
bits : 22 - 22 (1 bit)

ATAEND : CE-ATA command completion signal received
bits : 23 - 23 (1 bit)

CCRCERRC : CCRCERR flag clear bit
bits : 0 - 0 (1 bit)

DTCRCERRC : DTCRCERR flag clear bit
bits : 1 - 1 (1 bit)

CMDTMOUTC : CMDTMOUT flag clear bit
bits : 2 - 2 (1 bit)

DTTMOUTC : DTTMOUT flag clear bit
bits : 3 - 3 (1 bit)

TXUREC : TXURE flag clear bit
bits : 4 - 4 (1 bit)

RXOREC : RXORE flag clear bit
bits : 5 - 5 (1 bit)

CMDRECVC : CMDRECV flag clear bit
bits : 6 - 6 (1 bit)

CMDSENDC : CMDSEND flag clear bit
bits : 7 - 7 (1 bit)

DTENDC : DTEND flag clear bit
bits : 8 - 8 (1 bit)

STBITEC : STBITE flag clear bit
bits : 9 - 9 (1 bit)

DTBLKENDC : DTBLKEND flag clear bit
bits : 10 - 10 (1 bit)

SDIOINTC : SDIOINT flag clear bit
bits : 22 - 22 (1 bit)

ATAENDC : ATAEND flag clear bit
bits : 23 - 23 (1 bit)

CCRCERRIE : Command response CRC fail interrupt enable
bits : 0 - 0 (1 bit)

DTCRCERRIE : Data CRC fail interrupt enable
bits : 1 - 1 (1 bit)

CMDTMOUTIE : Command response timeout interrupt enable
bits : 2 - 2 (1 bit)

DTTMOUTIE : Data timeout interrupt enable
bits : 3 - 3 (1 bit)

TXUREIE : Transmit FIFO underrun error interrupt enable
bits : 4 - 4 (1 bit)

RXOREIE : Received FIFO overrun error interrupt enable
bits : 5 - 5 (1 bit)

CMDRECVIE : Command response received interrupt enable
bits : 6 - 6 (1 bit)

CMDSENDIE : Command sent interrupt enable
bits : 7 - 7 (1 bit)

DTENDIE : Data end interrupt enable
bits : 8 - 8 (1 bit)

STBITEIE : Start bit error interrupt enable
bits : 9 - 9 (1 bit)

DTBLKENDIE : Data block end interrupt enable
bits : 10 - 10 (1 bit)

CMDRUNIE : Command transmission interrupt enable
bits : 11 - 11 (1 bit)

TXRUNIE : Data transmission interrupt enable
bits : 12 - 12 (1 bit)

RXRUNIE : Data reception interrupt enable
bits : 13 - 13 (1 bit)

TFHIE : Transmit FIFO half empty interrupt enable
bits : 14 - 14 (1 bit)

RFHIE : Receive FIFO half full interrupt enable
bits : 15 - 15 (1 bit)

TFFIE : Transmit FIFO full interrupt enable
bits : 16 - 16 (1 bit)

RFFIE : Receive FIFO full interrupt enable
bits : 17 - 17 (1 bit)

TFEIE : Transmit FIFO empty interrupt enable
bits : 18 - 18 (1 bit)

RFEIE : Receive FIFO empty interrupt enable
bits : 19 - 19 (1 bit)

TXDTVALIE : Data valid in transmit FIFO interrupt enable
bits : 20 - 20 (1 bit)

RXDTVALIE : Data valid in receive FIFO interrupt enable
bits : 21 - 21 (1 bit)

SDIOINTIE : SD I/O interrupt received interrupt enable
bits : 22 - 22 (1 bit)

ATAENDIE : CE-ATA command completion signal received interrupt enable
bits : 23 - 23 (1 bit)

DIV : Clock division
bits : 0 - 7 (8 bit)

CLKEN : SDIO_CLK clock output enable bit
bits : 8 - 8 (1 bit)

CLKPWRSAV : SDIO_CLK clock dynamic switch on/off for power saving
bits : 9 - 9 (1 bit)

CLKBYP : Clock bypass enable bit
bits : 10 - 10 (1 bit)

BUSMODE : SDIO card bus mode control bit
bits : 11 - 12 (2 bit)

CLKEDGE : SDIO_CLK clock edge selection bit
bits : 13 - 13 (1 bit)

HWCLKEN : Hardware Clock Control enable bit
bits : 14 - 14 (1 bit)

FIFOCNT : FIFO counter
bits : 0 - 23 (24 bit)

CMDAGMT : SDIO card command argument
bits : 0 - 31 (32 bit)

FIFODT : Receive FIFO data or transmit FIFO data
bits : 0 - 31 (32 bit)

CMDIDX : Command index
bits : 0 - 5 (6 bit)

CMDRESP : Command response type bits
bits : 6 - 7 (2 bit)

INTWAIT : Interrupt wait instead of timeout
bits : 8 - 8 (1 bit)

WAITDEND : Waits for ends of data transfer
bits : 9 - 9 (1 bit)

CSMEN : Command state machine (CSM) enable bit
bits : 10 - 10 (1 bit)

SUSPEND : SD I/O suspend command(SD I/O only)
bits : 11 - 11 (1 bit)

ENCMDC : CMD completion signal enabled (CE-ATA only)
bits : 12 - 12 (1 bit)

NINTEN : No CE-ATA Interrupt (CE-ATA only)
bits : 13 - 13 (1 bit)

ATAEN : CE-ATA command enable(CE-ATA only)
bits : 14 - 14 (1 bit)