\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKPH : Clock Phase Selection
bits : 0 - 0 (1 bit)
CKPL : Clock polarity Selection
bits : 1 - 1 (1 bit)
MSTMOD : Master Mode Enable
bits : 2 - 2 (1 bit)
PSC : Master Clock Prescaler Selection
bits : 3 - 5 (3 bit)
SPIEN : SPI enable
bits : 6 - 6 (1 bit)
LF : LSB First Mode
bits : 7 - 7 (1 bit)
SWNSS : NSS Pin Selection In NSS Software Mode
bits : 8 - 8 (1 bit)
SWNSSEN : NSS Software Mode Selection
bits : 9 - 9 (1 bit)
RO : Receive only
bits : 10 - 10 (1 bit)
FF16 : Data frame format
bits : 11 - 11 (1 bit)
CRCNT : CRC Next Transfer
bits : 12 - 12 (1 bit)
CRCEN : CRC Calculation Enable
bits : 13 - 13 (1 bit)
BDOEN : Bidirectional Transmit output enable
bits : 14 - 14 (1 bit)
BDEN : Bidirectional enable
bits : 15 - 15 (1 bit)
CRC polynomial register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPR : CRC polynomial register
bits : 0 - 15 (16 bit)
RX CRC register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RCR : RX CRC register
bits : 0 - 15 (16 bit)
TX CRC register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TCR : Tx CRC register
bits : 0 - 15 (16 bit)
I2S control register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHLEN : Channel length (number of bits per audio channel)
bits : 0 - 0 (1 bit)
DTLEN : Data length
bits : 1 - 2 (2 bit)
CKPL : Idle state clock polarity
bits : 3 - 3 (1 bit)
I2SSTD : I2S standard selection
bits : 4 - 5 (2 bit)
PCMSMOD : PCM frame synchronization mode
bits : 7 - 7 (1 bit)
I2SOPMOD : I2S operation mode
bits : 8 - 9 (2 bit)
I2SEN : I2S Enable
bits : 10 - 10 (1 bit)
I2SSEL : I2S mode selection
bits : 11 - 11 (1 bit)
I2S prescaler register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Dividing factor for the prescaler
bits : 0 - 7 (8 bit)
OF : Odd factor for the prescaler
bits : 8 - 8 (1 bit)
MCKOEN : I2S_MCK output enable
bits : 9 - 9 (1 bit)
control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREN : Rx buffer DMA enable
bits : 0 - 0 (1 bit)
DMATEN : Transmit Buffer DMA Enable
bits : 1 - 1 (1 bit)
NSSDRV : Drive NSS Output
bits : 2 - 2 (1 bit)
ERRIE : Error interrupt enable
bits : 5 - 5 (1 bit)
RBNEIE : RX buffer not empty interrupt enable
bits : 6 - 6 (1 bit)
TBEIE : Tx buffer empty interrupt enable
bits : 7 - 7 (1 bit)
status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBNE : Receive Buffer Not Empty
bits : 0 - 0 (1 bit)
access : read-only
TBE : Transmit Buffer Empty
bits : 1 - 1 (1 bit)
access : read-only
I2SCH : I2S channel side
bits : 2 - 2 (1 bit)
access : read-only
TXURERR : Transmission underrun error bit
bits : 3 - 3 (1 bit)
access : read-only
CRCERR : SPI CRC Error Bit
bits : 4 - 4 (1 bit)
access : read-write
CONFERR : SPI Configuration error
bits : 5 - 5 (1 bit)
access : read-only
RXORERR : Reception Overrun Error Bit
bits : 6 - 6 (1 bit)
access : read-only
TRANS : Transmitting On-going Bit
bits : 7 - 7 (1 bit)
access : read-only
data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI_DATA : Data transfer register
bits : 0 - 15 (16 bit)
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