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TIMER

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTL0

INTF

SWEVG

CHCTL0_Output

CHCTL0_Input

CHCTL1_Output

CHCTL1_Input

CHCTL2

CNT

PSC

CAR

CH0CV

CH1CV

CH2CV

CTL1

CH3CV

DMACFG

DMATB

SMCFG

DMAINTEN


CTL0

control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL0 CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN UPDIS UPS SPM DIR CAM ARSE CKDIV

CEN : Counter enable
bits : 0 - 0 (1 bit)

UPDIS : Update disable
bits : 1 - 1 (1 bit)

UPS : Update source
bits : 2 - 2 (1 bit)

SPM : Single pulse mode
bits : 3 - 3 (1 bit)

DIR : Direction
bits : 4 - 4 (1 bit)

CAM : Counter aligns mode selection
bits : 5 - 6 (2 bit)

ARSE : Auto-reload shadow enable
bits : 7 - 7 (1 bit)

CKDIV : Clock division
bits : 8 - 9 (2 bit)


INTF

interrupt flag register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTF INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPIF CH0IF CH1IF CH2IF CH3IF TRGIF CH0OF CH1OF CH2OF CH3OF

UPIF : Update interrupt flag
bits : 0 - 0 (1 bit)

CH0IF : Channel 0 capture/compare interrupt flag
bits : 1 - 1 (1 bit)

CH1IF : Channel 1 capture/compare interrupt flag
bits : 2 - 2 (1 bit)

CH2IF : Channel 2 capture/compare interrupt enable
bits : 3 - 3 (1 bit)

CH3IF : Channel 3 capture/compare interrupt enable
bits : 4 - 4 (1 bit)

TRGIF : Trigger interrupt flag
bits : 6 - 6 (1 bit)

CH0OF : Channel 0 over capture flag
bits : 9 - 9 (1 bit)

CH1OF : Channel 1 over capture flag
bits : 10 - 10 (1 bit)

CH2OF : Channel 2 over capture flag
bits : 11 - 11 (1 bit)

CH3OF : Channel 3 over capture flag
bits : 12 - 12 (1 bit)


SWEVG

event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWEVG SWEVG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPG CH0G CH1G CH2G CH3G TRGG

UPG : Update generation
bits : 0 - 0 (1 bit)

CH0G : Channel 0 capture or compare event generation
bits : 1 - 1 (1 bit)

CH1G : Channel 1 capture or compare event generation
bits : 2 - 2 (1 bit)

CH2G : Channel 2 capture or compare event generation
bits : 3 - 3 (1 bit)

CH3G : Channel 3 capture or compare event generation
bits : 4 - 4 (1 bit)

TRGG : Trigger event generation
bits : 6 - 6 (1 bit)


CHCTL0_Output

Channel control register 0 (output mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTL0_Output CHCTL0_Output read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0MS CH0COMFEN CH0COMSEN CH0COMCTL CH0COMCEN CH1MS CH1COMFEN CH1COMSEN CH1COMCTL CH1COMCEN

CH0MS : Channel 0 I/O mode selection
bits : 0 - 1 (2 bit)

CH0COMFEN : Channel 0 output compare fast enable
bits : 2 - 2 (1 bit)

CH0COMSEN : Channel 0 compare output shadow enable
bits : 3 - 3 (1 bit)

CH0COMCTL : Channel 0 compare output control
bits : 4 - 6 (3 bit)

CH0COMCEN : Channel 0 output compare clear enable
bits : 7 - 7 (1 bit)

CH1MS : Channel 1 mode selection
bits : 8 - 9 (2 bit)

CH1COMFEN : Channel 1 output compare fast enable
bits : 10 - 10 (1 bit)

CH1COMSEN : Channel 1 output compare shadow enable
bits : 11 - 11 (1 bit)

CH1COMCTL : Channel 1 compare output control
bits : 12 - 14 (3 bit)

CH1COMCEN : Channel 1 output compare clear enable
bits : 15 - 15 (1 bit)


CHCTL0_Input

Channel control register 0 (input mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CHCTL0_Output
reset_Mask : 0x0

CHCTL0_Input CHCTL0_Input read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0MS CH0CAPPSC CH0CAPFLT CH1MS CH1CAPPSC CH1CAPFLT

CH0MS : Channel 0 mode selection
bits : 0 - 1 (2 bit)

CH0CAPPSC : Channel 0 input capture prescaler
bits : 2 - 3 (2 bit)

CH0CAPFLT : Channel 0 input capture filter control
bits : 4 - 7 (4 bit)

CH1MS : Channel 1 mode selection
bits : 8 - 9 (2 bit)

CH1CAPPSC : Channel 1 input capture prescaler
bits : 10 - 11 (2 bit)

CH1CAPFLT : Channel 1 input capture filter control
bits : 12 - 15 (4 bit)


CHCTL1_Output

Channel control register 1 (output mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTL1_Output CHCTL1_Output read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH2MS CH2COMFEN CH2COMSEN CH2COMCTL CH2COMCEN CH3MS CH3COMFEN CH3COMSEN CH3COMCTL CH3COMCEN

CH2MS : Channel 2 I/O mode selection
bits : 0 - 1 (2 bit)

CH2COMFEN : Channel 2 output compare fast enable
bits : 2 - 2 (1 bit)

CH2COMSEN : Channel 2 compare output shadow enable
bits : 3 - 3 (1 bit)

CH2COMCTL : Channel 2 compare output control
bits : 4 - 6 (3 bit)

CH2COMCEN : Channel 2 output compare clear enable
bits : 7 - 7 (1 bit)

CH3MS : Channel 3 mode selection
bits : 8 - 9 (2 bit)

CH3COMFEN : Channel 3 output compare fast enable
bits : 10 - 10 (1 bit)

CH3COMSEN : Channel 3 output compare shadow enable
bits : 11 - 11 (1 bit)

CH3COMCTL : Channel 3 compare output control
bits : 12 - 14 (3 bit)

CH3COMCEN : Channel 3 output compare clear enable
bits : 15 - 15 (1 bit)


CHCTL1_Input

Channel control register 1 (input mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CHCTL1_Output
reset_Mask : 0x0

CHCTL1_Input CHCTL1_Input read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH2MS CH2CAPPSC CH2CAPFLT CH3MS CH3CAPPSC CH3CAPFLT

CH2MS : Channel 2 mode selection
bits : 0 - 1 (2 bit)

CH2CAPPSC : Channel 2 input capture prescaler
bits : 2 - 3 (2 bit)

CH2CAPFLT : Channel 2 input capture filter control
bits : 4 - 7 (4 bit)

CH3MS : Channel 3 mode selection
bits : 8 - 9 (2 bit)

CH3CAPPSC : Channel 3 input capture prescaler
bits : 10 - 11 (2 bit)

CH3CAPFLT : Channel 3 input capture filter control
bits : 12 - 15 (4 bit)


CHCTL2

Channel control register 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTL2 CHCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0EN CH0P CH1EN CH1P CH2EN CH2P CH3EN CH3P

CH0EN : Channel 0 capture/compare function enable
bits : 0 - 0 (1 bit)

CH0P : Channel 0 capture/compare function polarity
bits : 1 - 1 (1 bit)

CH1EN : Channel 1 capture/compare function enable
bits : 4 - 4 (1 bit)

CH1P : Channel 1 capture/compare function polarity
bits : 5 - 5 (1 bit)

CH2EN : Channel 2 capture/compare function enable
bits : 8 - 8 (1 bit)

CH2P : Channel 2 capture/compare function polarity
bits : 9 - 9 (1 bit)

CH3EN : Channel 3 capture/compare function enable
bits : 12 - 12 (1 bit)

CH3P : Channel 3 capture/compare function polarity
bits : 13 - 13 (1 bit)


CNT

Counter register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : counter value
bits : 0 - 15 (16 bit)


PSC

Prescaler register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSC PSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC

PSC : Prescaler value of the counter clock
bits : 0 - 15 (16 bit)


CAR

Counter auto reload register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAR CAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARL

CARL : Counter auto reload value
bits : 0 - 15 (16 bit)


CH0CV

Channel 0 capture/compare value register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0CV CH0CV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0VAL

CH0VAL : Capture or compare value of channel 0
bits : 0 - 15 (16 bit)


CH1CV

Channel 1 capture/compare value register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CV CH1CV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1VAL

CH1VAL : Capture or compare value of channel1
bits : 0 - 15 (16 bit)


CH2CV

Channel 2 capture/compare value register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2CV CH2CV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH2VAL

CH2VAL : Capture or compare value of channel 2
bits : 0 - 15 (16 bit)


CTL1

control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL1 CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAS MMC TI0S

DMAS : DMA request source selection
bits : 3 - 3 (1 bit)

MMC : Master mode control
bits : 4 - 6 (3 bit)

TI0S : Channel 0 trigger input selection
bits : 7 - 7 (1 bit)


CH3CV

Channel 3 capture/compare value register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3CV CH3CV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH3VAL

CH3VAL : Capture or compare value of channel 3
bits : 0 - 15 (16 bit)


DMACFG

DMA configuration register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACFG DMACFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMATA DMATC

DMATA : DMA transfer access start address
bits : 0 - 4 (5 bit)

DMATC : DMA transfer count
bits : 8 - 12 (5 bit)


DMATB

DMA transfer buffer register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMATB DMATB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMATB

DMATB : DMA transfer buffer
bits : 0 - 15 (16 bit)


SMCFG

slave mode control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMCFG SMCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMC TRGS MSM ETFC ETPSC SMC1 ETP

SMC : Slave mode control
bits : 0 - 2 (3 bit)

TRGS : Trigger selection
bits : 4 - 6 (3 bit)

MSM : Master-slave mode
bits : 7 - 7 (1 bit)

ETFC : External trigger filter control
bits : 8 - 11 (4 bit)

ETPSC : External trigger prescaler
bits : 12 - 13 (2 bit)

SMC1 : Part of SMC for enable External clock mode1
bits : 14 - 14 (1 bit)

ETP : External trigger polarity
bits : 15 - 15 (1 bit)


DMAINTEN

DMA/Interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAINTEN DMAINTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPIE CH0IE CH1IE CH2IE CH3IE TRGIE UPDEN CH0DEN CH1DEN CH2DEN CH3DEN TRGDEN

UPIE : Update interrupt enable
bits : 0 - 0 (1 bit)

CH0IE : Channel 0 capture/compare interrupt enable
bits : 1 - 1 (1 bit)

CH1IE : Channel 1 capture/compare interrupt enable
bits : 2 - 2 (1 bit)

CH2IE : Channel 2 capture/compare interrupt enable
bits : 3 - 3 (1 bit)

CH3IE : Channel 3 capture/compare interrupt enable
bits : 4 - 4 (1 bit)

TRGIE : Trigger interrupt enable
bits : 6 - 6 (1 bit)

UPDEN : Update DMA request enable
bits : 8 - 8 (1 bit)

CH0DEN : Channel 0 capture/compare DMA request enable
bits : 9 - 9 (1 bit)

CH1DEN : Channel 1 capture/compare DMA request enable
bits : 10 - 10 (1 bit)

CH2DEN : Channel 2 capture/compare DMA request enable
bits : 11 - 11 (1 bit)

CH3DEN : Channel 3 capture/compare DMA request enable
bits : 12 - 12 (1 bit)

TRGDEN : Trigger DMA request enable
bits : 14 - 14 (1 bit)



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