\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
endpoint 0 register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP_ADDR : Endpoint address
bits : 0 - 3 (4 bit)
TX_STA : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
TX_DTG : Data PID Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
TX_ST : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
EP_KCTL : Endpoint kind
bits : 8 - 8 (1 bit)
EP_CTL : Endpoint type
bits : 9 - 10 (2 bit)
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
RX_STA : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
RX_DTG : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
RX_ST : Correct transfer for reception
bits : 15 - 15 (1 bit)
endpoint 4 register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP_ADDR : Endpoint address
bits : 0 - 3 (4 bit)
TX_STA : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
TX_DTG : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
TX_ST : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
EP_KCTL : Endpoint kind
bits : 8 - 8 (1 bit)
EP_CTL : Endpoint type
bits : 9 - 10 (2 bit)
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
RX_STA : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
RX_DTG : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
RX_ST : Correct transfer for reception
bits : 15 - 15 (1 bit)
endpoint 5 register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP_ADDR : Endpoint address
bits : 0 - 3 (4 bit)
TX_STA : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
TX_DTG : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
TX_ST : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
EP_KCTL : Endpoint kind
bits : 8 - 8 (1 bit)
EP_CTL : Endpoint type
bits : 9 - 10 (2 bit)
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
RX_STA : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
RX_DTG : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
RX_ST : Correct transfer for reception
bits : 15 - 15 (1 bit)
endpoint 6 register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP_ADDR : Endpoint address
bits : 0 - 3 (4 bit)
TX_STA : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
TX_DTG : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
TX_ST : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
EP_KCTL : Endpoint kind
bits : 8 - 8 (1 bit)
EP_CTL : Endpoint type
bits : 9 - 10 (2 bit)
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
RX_STA : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
RX_DTG : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
RX_ST : Correct transfer for reception
bits : 15 - 15 (1 bit)
endpoint 7 register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP_ADDR : Endpoint address
bits : 0 - 3 (4 bit)
TX_STA : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
TX_DTG : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
TX_ST : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
EP_KCTL : Endpoint kind
bits : 8 - 8 (1 bit)
EP_CTL : Endpoint type
bits : 9 - 10 (2 bit)
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
RX_STA : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
RX_DTG : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
RX_ST : Correct transfer for reception
bits : 15 - 15 (1 bit)
endpoint 1 register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP_ADDR : Endpoint address
bits : 0 - 3 (4 bit)
TX_STA : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
TX_DTG : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
TX_ST : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
EP_KCTL : Endpoint kind
bits : 8 - 8 (1 bit)
EP_CTL : Endpoint type
bits : 9 - 10 (2 bit)
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
RX_STA : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
RX_DTG : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
RX_ST : Correct transfer for reception
bits : 15 - 15 (1 bit)
control register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETRST : Set reset
bits : 0 - 0 (1 bit)
CLOSE : Close state
bits : 1 - 1 (1 bit)
LOWM : Low-power mode
bits : 2 - 2 (1 bit)
SETSPS : Set suspend
bits : 3 - 3 (1 bit)
RSREQ : Resume request
bits : 4 - 4 (1 bit)
ESOFIE : Expected start of frame interrupt enable
bits : 8 - 8 (1 bit)
SOFIE : Start of frame interrupt mask
bits : 9 - 9 (1 bit)
RSTIE : USB reset interrupt mask
bits : 10 - 10 (1 bit)
SPSIE : Suspend mode interrupt mask
bits : 11 - 11 (1 bit)
WKUPIE : Wakeup interrupt enable
bits : 12 - 12 (1 bit)
ERRIE : Error interrupt mask
bits : 13 - 13 (1 bit)
PMOUIE : Packet memory area over / underrun interrupt enable
bits : 14 - 14 (1 bit)
STIE : Successful transfer interrupt enable
bits : 15 - 15 (1 bit)
interrupt flag register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPNUM : Endpoint Identifier
bits : 0 - 3 (4 bit)
access : read-only
DIR : Direction of transaction
bits : 4 - 4 (1 bit)
access : read-only
ESOFIF : Expected start of frame interrupt flag
bits : 8 - 8 (1 bit)
access : read-write
SOFIF : start of frame interrupt flag
bits : 9 - 9 (1 bit)
access : read-write
RSTIF : reset interrupt flag
bits : 10 - 10 (1 bit)
access : read-write
SPSIF : Suspend mode interrupt flag
bits : 11 - 11 (1 bit)
access : read-write
WKUPIF : Wakeup interrupt flag
bits : 12 - 12 (1 bit)
access : read-write
ERRIF : Error interrupt flag
bits : 13 - 13 (1 bit)
access : read-write
PMOUIF : Packet memory area over / underrun interrupt flag
bits : 14 - 14 (1 bit)
access : read-write
STIF : Successful transfer interrupt flag
bits : 15 - 15 (1 bit)
access : read-only
Status register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FCNT : Frame number counter
bits : 0 - 10 (11 bit)
SOFLN : Lost SOF number
bits : 11 - 12 (2 bit)
LOCK : Locked the USB
bits : 13 - 13 (1 bit)
RX_DM : Receive data - line status
bits : 14 - 14 (1 bit)
RX_DP : Receive data + line status
bits : 15 - 15 (1 bit)
device address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBDAR : Device address
bits : 0 - 6 (7 bit)
USBEN : USB device enable
bits : 7 - 7 (1 bit)
Buffer address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BAR : Buffer address
bits : 3 - 15 (13 bit)
endpoint 2 register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP_ADDR : Endpoint address
bits : 0 - 3 (4 bit)
TX_STA : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
TX_DTG : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
TX_ST : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
EP_KCTL : Endpoint kind
bits : 8 - 8 (1 bit)
EP_CTL : Endpoint type
bits : 9 - 10 (2 bit)
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
RX_STA : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
RX_DTG : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
RX_ST : Correct transfer for reception
bits : 15 - 15 (1 bit)
endpoint 3 register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP_ADDR : Endpoint address
bits : 0 - 3 (4 bit)
TX_STA : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
TX_DTG : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
TX_ST : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
EP_KCTL : Endpoint kind
bits : 8 - 8 (1 bit)
EP_CTL : Endpoint type
bits : 9 - 10 (2 bit)
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
RX_STA : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
RX_DTG : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
RX_ST : Correct transfer for reception
bits : 15 - 15 (1 bit)
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