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USBD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

EP0CS

EP4CS

EP5CS

EP6CS

EP7CS

EP1CS

CTL

INTF

STAT

DADDR

BADDR

EP2CS

EP3CS


EP0CS

endpoint 0 register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP0CS EP0CS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP_ADDR TX_STA TX_DTG TX_ST EP_KCTL EP_CTL SETUP RX_STA RX_DTG RX_ST

EP_ADDR : Endpoint address
bits : 0 - 3 (4 bit)

TX_STA : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)

TX_DTG : Data PID Toggle, for transmission transfers
bits : 6 - 6 (1 bit)

TX_ST : Correct Transfer for transmission
bits : 7 - 7 (1 bit)

EP_KCTL : Endpoint kind
bits : 8 - 8 (1 bit)

EP_CTL : Endpoint type
bits : 9 - 10 (2 bit)

SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)

RX_STA : Status bits, for reception transfers
bits : 12 - 13 (2 bit)

RX_DTG : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)

RX_ST : Correct transfer for reception
bits : 15 - 15 (1 bit)


EP4CS

endpoint 4 register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP4CS EP4CS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP_ADDR TX_STA TX_DTG TX_ST EP_KCTL EP_CTL SETUP RX_STA RX_DTG RX_ST

EP_ADDR : Endpoint address
bits : 0 - 3 (4 bit)

TX_STA : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)

TX_DTG : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)

TX_ST : Correct Transfer for transmission
bits : 7 - 7 (1 bit)

EP_KCTL : Endpoint kind
bits : 8 - 8 (1 bit)

EP_CTL : Endpoint type
bits : 9 - 10 (2 bit)

SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)

RX_STA : Status bits, for reception transfers
bits : 12 - 13 (2 bit)

RX_DTG : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)

RX_ST : Correct transfer for reception
bits : 15 - 15 (1 bit)


EP5CS

endpoint 5 register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP5CS EP5CS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP_ADDR TX_STA TX_DTG TX_ST EP_KCTL EP_CTL SETUP RX_STA RX_DTG RX_ST

EP_ADDR : Endpoint address
bits : 0 - 3 (4 bit)

TX_STA : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)

TX_DTG : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)

TX_ST : Correct Transfer for transmission
bits : 7 - 7 (1 bit)

EP_KCTL : Endpoint kind
bits : 8 - 8 (1 bit)

EP_CTL : Endpoint type
bits : 9 - 10 (2 bit)

SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)

RX_STA : Status bits, for reception transfers
bits : 12 - 13 (2 bit)

RX_DTG : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)

RX_ST : Correct transfer for reception
bits : 15 - 15 (1 bit)


EP6CS

endpoint 6 register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP6CS EP6CS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP_ADDR TX_STA TX_DTG TX_ST EP_KCTL EP_CTL SETUP RX_STA RX_DTG RX_ST

EP_ADDR : Endpoint address
bits : 0 - 3 (4 bit)

TX_STA : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)

TX_DTG : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)

TX_ST : Correct Transfer for transmission
bits : 7 - 7 (1 bit)

EP_KCTL : Endpoint kind
bits : 8 - 8 (1 bit)

EP_CTL : Endpoint type
bits : 9 - 10 (2 bit)

SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)

RX_STA : Status bits, for reception transfers
bits : 12 - 13 (2 bit)

RX_DTG : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)

RX_ST : Correct transfer for reception
bits : 15 - 15 (1 bit)


EP7CS

endpoint 7 register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP7CS EP7CS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP_ADDR TX_STA TX_DTG TX_ST EP_KCTL EP_CTL SETUP RX_STA RX_DTG RX_ST

EP_ADDR : Endpoint address
bits : 0 - 3 (4 bit)

TX_STA : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)

TX_DTG : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)

TX_ST : Correct Transfer for transmission
bits : 7 - 7 (1 bit)

EP_KCTL : Endpoint kind
bits : 8 - 8 (1 bit)

EP_CTL : Endpoint type
bits : 9 - 10 (2 bit)

SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)

RX_STA : Status bits, for reception transfers
bits : 12 - 13 (2 bit)

RX_DTG : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)

RX_ST : Correct transfer for reception
bits : 15 - 15 (1 bit)


EP1CS

endpoint 1 register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP1CS EP1CS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP_ADDR TX_STA TX_DTG TX_ST EP_KCTL EP_CTL SETUP RX_STA RX_DTG RX_ST

EP_ADDR : Endpoint address
bits : 0 - 3 (4 bit)

TX_STA : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)

TX_DTG : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)

TX_ST : Correct Transfer for transmission
bits : 7 - 7 (1 bit)

EP_KCTL : Endpoint kind
bits : 8 - 8 (1 bit)

EP_CTL : Endpoint type
bits : 9 - 10 (2 bit)

SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)

RX_STA : Status bits, for reception transfers
bits : 12 - 13 (2 bit)

RX_DTG : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)

RX_ST : Correct transfer for reception
bits : 15 - 15 (1 bit)


CTL

control register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETRST CLOSE LOWM SETSPS RSREQ ESOFIE SOFIE RSTIE SPSIE WKUPIE ERRIE PMOUIE STIE

SETRST : Set reset
bits : 0 - 0 (1 bit)

CLOSE : Close state
bits : 1 - 1 (1 bit)

LOWM : Low-power mode
bits : 2 - 2 (1 bit)

SETSPS : Set suspend
bits : 3 - 3 (1 bit)

RSREQ : Resume request
bits : 4 - 4 (1 bit)

ESOFIE : Expected start of frame interrupt enable
bits : 8 - 8 (1 bit)

SOFIE : Start of frame interrupt mask
bits : 9 - 9 (1 bit)

RSTIE : USB reset interrupt mask
bits : 10 - 10 (1 bit)

SPSIE : Suspend mode interrupt mask
bits : 11 - 11 (1 bit)

WKUPIE : Wakeup interrupt enable
bits : 12 - 12 (1 bit)

ERRIE : Error interrupt mask
bits : 13 - 13 (1 bit)

PMOUIE : Packet memory area over / underrun interrupt enable
bits : 14 - 14 (1 bit)

STIE : Successful transfer interrupt enable
bits : 15 - 15 (1 bit)


INTF

interrupt flag register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTF INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPNUM DIR ESOFIF SOFIF RSTIF SPSIF WKUPIF ERRIF PMOUIF STIF

EPNUM : Endpoint Identifier
bits : 0 - 3 (4 bit)
access : read-only

DIR : Direction of transaction
bits : 4 - 4 (1 bit)
access : read-only

ESOFIF : Expected start of frame interrupt flag
bits : 8 - 8 (1 bit)
access : read-write

SOFIF : start of frame interrupt flag
bits : 9 - 9 (1 bit)
access : read-write

RSTIF : reset interrupt flag
bits : 10 - 10 (1 bit)
access : read-write

SPSIF : Suspend mode interrupt flag
bits : 11 - 11 (1 bit)
access : read-write

WKUPIF : Wakeup interrupt flag
bits : 12 - 12 (1 bit)
access : read-write

ERRIF : Error interrupt flag
bits : 13 - 13 (1 bit)
access : read-write

PMOUIF : Packet memory area over / underrun interrupt flag
bits : 14 - 14 (1 bit)
access : read-write

STIF : Successful transfer interrupt flag
bits : 15 - 15 (1 bit)
access : read-only


STAT

Status register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCNT SOFLN LOCK RX_DM RX_DP

FCNT : Frame number counter
bits : 0 - 10 (11 bit)

SOFLN : Lost SOF number
bits : 11 - 12 (2 bit)

LOCK : Locked the USB
bits : 13 - 13 (1 bit)

RX_DM : Receive data - line status
bits : 14 - 14 (1 bit)

RX_DP : Receive data + line status
bits : 15 - 15 (1 bit)


DADDR

device address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DADDR DADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBDAR USBEN

USBDAR : Device address
bits : 0 - 6 (7 bit)

USBEN : USB device enable
bits : 7 - 7 (1 bit)


BADDR

Buffer address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BADDR BADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BAR

BAR : Buffer address
bits : 3 - 15 (13 bit)


EP2CS

endpoint 2 register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP2CS EP2CS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP_ADDR TX_STA TX_DTG TX_ST EP_KCTL EP_CTL SETUP RX_STA RX_DTG RX_ST

EP_ADDR : Endpoint address
bits : 0 - 3 (4 bit)

TX_STA : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)

TX_DTG : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)

TX_ST : Correct Transfer for transmission
bits : 7 - 7 (1 bit)

EP_KCTL : Endpoint kind
bits : 8 - 8 (1 bit)

EP_CTL : Endpoint type
bits : 9 - 10 (2 bit)

SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)

RX_STA : Status bits, for reception transfers
bits : 12 - 13 (2 bit)

RX_DTG : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)

RX_ST : Correct transfer for reception
bits : 15 - 15 (1 bit)


EP3CS

endpoint 3 register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP3CS EP3CS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP_ADDR TX_STA TX_DTG TX_ST EP_KCTL EP_CTL SETUP RX_STA RX_DTG RX_ST

EP_ADDR : Endpoint address
bits : 0 - 3 (4 bit)

TX_STA : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)

TX_DTG : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)

TX_ST : Correct Transfer for transmission
bits : 7 - 7 (1 bit)

EP_KCTL : Endpoint kind
bits : 8 - 8 (1 bit)

EP_CTL : Endpoint type
bits : 9 - 10 (2 bit)

SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)

RX_STA : Status bits, for reception transfers
bits : 12 - 13 (2 bit)

RX_DTG : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)

RX_ST : Correct transfer for reception
bits : 15 - 15 (1 bit)



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