\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
wait state counter register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WSCNT : wait state counter register
bits : 0 - 2 (3 bit)
Control register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG : Main flash program for bank0 command bit
bits : 0 - 0 (1 bit)
PER : Main flash page erase for bank0 command bit
bits : 1 - 1 (1 bit)
MER : Main flash mass erase for bank0 command bit
bits : 2 - 2 (1 bit)
OBPG : Option bytes program command bit
bits : 4 - 4 (1 bit)
OBER : Option bytes erase command bit
bits : 5 - 5 (1 bit)
START : Send erase command to FMC bit
bits : 6 - 6 (1 bit)
LK : FMC_CTL0 lock bit
bits : 7 - 7 (1 bit)
OBWEN : Option byte erase/program enable bit
bits : 9 - 9 (1 bit)
ERRIE : Error interrupt enable bit
bits : 10 - 10 (1 bit)
ENDIE : End of operation interrupt enable bit
bits : 12 - 12 (1 bit)
Product ID register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PID : Product reserved ID code register
bits : 0 - 31 (32 bit)
Address register 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : Flash erase/program command address bits
bits : 0 - 31 (32 bit)
Option byte status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OBERR : Option bytes read error bit
bits : 0 - 0 (1 bit)
SPC : Option bytes security protection code
bits : 1 - 1 (1 bit)
USER : Store USER of option bytes block after system reset
bits : 2 - 9 (8 bit)
DATA : Store DATA[15:0] of option bytes block after system reset
bits : 10 - 25 (16 bit)
Erase/Program Protection register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WP : Store WP[31:0] of option bytes block after system reset
bits : 0 - 31 (32 bit)
Unlock key register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : FMC_CTL0 unlock key
bits : 0 - 31 (32 bit)
Unlock key register 1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : FMC_CTL1 unlock register
bits : 0 - 31 (32 bit)
Status register 1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSY : The flash is busy bit
bits : 0 - 0 (1 bit)
access : read-only
PGERR : Program error flag bit
bits : 2 - 2 (1 bit)
access : read-write
WPERR : Erase/Program protection error flag bit
bits : 4 - 4 (1 bit)
access : read-write
ENDF : End of operation flag bit
bits : 5 - 5 (1 bit)
access : read-write
Control register 1
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG : Main flash program for bank1 command bit
bits : 0 - 0 (1 bit)
PER : Main flash page erase for bank1 command bit
bits : 1 - 1 (1 bit)
MER : Main flash mass erase for bank1 command bit
bits : 2 - 2 (1 bit)
START : Send erase command to FMC bit
bits : 6 - 6 (1 bit)
LK : FMC_CTL1 lock bit
bits : 7 - 7 (1 bit)
ERRIE : Error interrupt enable bit
bits : 10 - 10 (1 bit)
ENDIE : End of operation interrupt enable bit
bits : 12 - 12 (1 bit)
Address register 1
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : Flash erase/program command address bits
bits : 0 - 31 (32 bit)
Option byte unlock key register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OBKEY : FMC_ CTL0 option byte operation unlock register
bits : 0 - 31 (32 bit)
Status register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSY : The flash is busy bit
bits : 0 - 0 (1 bit)
access : read-only
PGERR : Program error flag bit
bits : 2 - 2 (1 bit)
access : read-write
WPERR : Erase/Program protection error flag bit
bits : 4 - 4 (1 bit)
access : read-write
ENDF : End of operation flag bit
bits : 5 - 5 (1 bit)
access : read-write
Wait state enable register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WSEN : FMC wait state enable register
bits : 0 - 0 (1 bit)
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