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CEC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTL

INTF

INTEN

CFG

TDATA

RDATA


CTL

control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CECEN STAOM ENDOM

CECEN : Enable/disable HDMI-CEC controller
bits : 0 - 0 (1 bit)

STAOM : Start of sending a message
bits : 1 - 1 (1 bit)

ENDOM : ENDOM bit value in the next frame in TX mode
bits : 2 - 2 (1 bit)


INTF

Interrupt Flag Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTF INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BR REND RO BRE BPSE BPLE RAE ARBF TBR TEND TU TERR TAERR

BR : Byte received
bits : 0 - 0 (1 bit)

REND : End of Reception
bits : 1 - 1 (1 bit)

RO : RX Overrun
bits : 2 - 2 (1 bit)

BRE : Bit Rising Error
bits : 3 - 3 (1 bit)

BPSE : Bit Period Short Error
bits : 4 - 4 (1 bit)

BPLE : Bit Period Long Error
bits : 5 - 5 (1 bit)

RAE : Rx ACK Error
bits : 6 - 6 (1 bit)

ARBF : Arbitration fail
bits : 7 - 7 (1 bit)

TBR : Tx-Byte data request
bits : 8 - 8 (1 bit)

TEND : Transmission successfully end
bits : 9 - 9 (1 bit)

TU : Tx data buffer underrun
bits : 10 - 10 (1 bit)

TERR : Tx-Error
bits : 11 - 11 (1 bit)

TAERR : Tx ACK Error flag
bits : 12 - 12 (1 bit)


INTEN

interrupt enable register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRIE RENDIE ROIE BREIE BPSEIE BPLEIE RAEIE ARBFIE TBRIE TXENDIE TUIE TERRIE TAERRIE

BRIE : BR Interrupt Enable
bits : 0 - 0 (1 bit)

RENDIE : REND Interrupt Enable
bits : 1 - 1 (1 bit)

ROIE : RO Interrupt Enable
bits : 2 - 2 (1 bit)

BREIE : BRE Interrupt Enable
bits : 3 - 3 (1 bit)

BPSEIE : BPSE Interrupt Enable
bits : 4 - 4 (1 bit)

BPLEIE : BPLE Interrupt Enable
bits : 5 - 5 (1 bit)

RAEIE : RAE Interrupt Enable
bits : 6 - 6 (1 bit)

ARBFIE : ARBF Interrupt Enable
bits : 7 - 7 (1 bit)

TBRIE : TBR Interrupt Enable
bits : 8 - 8 (1 bit)

TXENDIE : TEND Interrupt Enable
bits : 9 - 9 (1 bit)

TUIE : TU Interrupt Enable
bits : 10 - 10 (1 bit)

TERRIE : TERR Interrupt Enable
bits : 11 - 11 (1 bit)

TAERRIE : TAERR Interrupt Enable
bits : 12 - 12 (1 bit)


CFG

Configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFT RTOL BRES BREG BPLEG BCNG SFTOPT OAD LMEN

SFT : Signal Free Time
bits : 0 - 2 (3 bit)

RTOL : Reception bit timing tolerance
bits : 3 - 3 (1 bit)

BRES : Whether stop receive message when detected RBRE
bits : 4 - 4 (1 bit)

BREG : Generate Error-bit when detected RBRE in singlecast
bits : 5 - 5 (1 bit)

BPLEG : Generate Error-bit when detected RLBPE in singlecast
bits : 6 - 6 (1 bit)

BCNG : Do not generate Error-bit in broadcast message
bits : 7 - 7 (1 bit)

SFTOPT : The SFT start option
bits : 8 - 8 (1 bit)

OAD : Own Address
bits : 16 - 30 (15 bit)

LMEN : Listen mode enable
bits : 31 - 31 (1 bit)


TDATA

Transmit data register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TDATA TDATA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDATA

TDATA : Tx Data register
bits : 0 - 7 (8 bit)


RDATA

Receive data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RDATA RDATA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATA

RDATA : Receive data register
bits : 0 - 7 (8 bit)



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