\n
address_offset : 0x0 Bytes (0x0)
size : 0x300 byte (0x0)
mem_usage : registers
protection :
control and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP0EN : CMP0 enable
bits : 0 - 0 (1 bit)
access : read-write
CMP0SW : CMP0 switch
bits : 1 - 1 (1 bit)
access : read-write
CMP0M : CMP0 mode
bits : 2 - 3 (2 bit)
access : read-write
CMP0MSEL : CMP0_M input selection
bits : 4 - 6 (3 bit)
access : read-write
CMP0OSEL : Comparator 0 output selection
bits : 8 - 10 (3 bit)
access : read-write
CMP0PL : Polarity of CMP0 output
bits : 11 - 11 (1 bit)
access : read-write
CMP0HST : CMP0 hysteresis
bits : 12 - 13 (2 bit)
access : read-write
CMP0O : CMP0 output
bits : 14 - 14 (1 bit)
access : read-only
CMP0LK : CMP0 lock
bits : 15 - 15 (1 bit)
access : read-write
CMP1EN : CMP1 enable
bits : 16 - 16 (1 bit)
access : read-write
CMP1M : CMP1 mode
bits : 18 - 19 (2 bit)
access : read-write
CMP1MSEL : CMP1_M input selection
bits : 20 - 22 (3 bit)
access : read-write
WNDEN : Window mode enable
bits : 23 - 23 (1 bit)
access : read-write
CMP1OSEL : CMP1 output selection
bits : 24 - 26 (3 bit)
access : read-write
CMP1PL : Polarity of CMP1 output
bits : 27 - 27 (1 bit)
access : read-write
CMP1HST : CMP1 hysteresis
bits : 28 - 29 (2 bit)
access : read-write
CMP1O : CMP1 output
bits : 30 - 30 (1 bit)
access : read-only
CMP1LK : CMP1 lock
bits : 31 - 31 (1 bit)
access : read-write
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