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DMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

INTF

CH0PADDR

CH0MADDR

CH1CTL0

CH1CNT

CH1PADDR

CH1MADDR

CH2CTL0

CH2CNT

CH2PADDR

CH2MADDR

INTC

CH3CTL0

CH3CNT

CH3PADDR

CH3MADDR

CH4CTL0

CH4CNT

CH4PADDR

CH4MADDR

CH5CTL0

CH5CNT

CH5PADDR

CH5MADDR

CH0CTL0

CH6CTL0

CH6CNT

CH6PADDR

CH6MADDR

CH0CNT


INTF

DMA interrupt flag register (DMA_INTF)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTF INTF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GIF0 FTFIF0 HTFIF0 ERRIF0 GIF1 FTFIF1 HTFIF1 ERRIF1 GIF2 FTFIF2 HTFIF2 ERRIF2 GIF3 FTFIF3 HTFIF3 ERRIF3 GIF4 FTFIF4 HTFIF4 ERRIF4 GIF5 FTFIF5 HTFIF5 ERRIF5 GIF6 FTFIF6 HTFIF6 ERRIF6

GIF0 : Global interrupt flag of channel 0
bits : 0 - 0 (1 bit)

FTFIF0 : Full transfer finish flag of channel 0
bits : 1 - 1 (1 bit)

HTFIF0 : Half transfer finish flag of channel 0
bits : 2 - 2 (1 bit)

ERRIF0 : Error flag of channel 0
bits : 3 - 3 (1 bit)

GIF1 : Global interrupt flag of channel 1
bits : 4 - 4 (1 bit)

FTFIF1 : Full transfer finish flag of channel 1
bits : 5 - 5 (1 bit)

HTFIF1 : Half transfer finish flag of channel 1
bits : 6 - 6 (1 bit)

ERRIF1 : Error flag of channel 1
bits : 7 - 7 (1 bit)

GIF2 : Global interrupt flag of channel 2
bits : 8 - 8 (1 bit)

FTFIF2 : Full transfer finish flag of channel 2
bits : 9 - 9 (1 bit)

HTFIF2 : Half transfer finish flag of channel 2
bits : 10 - 10 (1 bit)

ERRIF2 : Error flag of channel 2
bits : 11 - 11 (1 bit)

GIF3 : Global interrupt flag of channel 3
bits : 12 - 12 (1 bit)

FTFIF3 : Full transfer finish flag of channel 3
bits : 13 - 13 (1 bit)

HTFIF3 : Half transfer finish flag of channel 3
bits : 14 - 14 (1 bit)

ERRIF3 : Error flag of channel 3
bits : 15 - 15 (1 bit)

GIF4 : Global interrupt flag of channel 4
bits : 16 - 16 (1 bit)

FTFIF4 : Full transfer finish flag of channel 4
bits : 17 - 17 (1 bit)

HTFIF4 : Half transfer finish flag of channel 4
bits : 18 - 18 (1 bit)

ERRIF4 : Error flag of channel 4
bits : 19 - 19 (1 bit)

GIF5 : Global interrupt flag of channel 5
bits : 20 - 20 (1 bit)

FTFIF5 : Full transfer finish flag of channel 5
bits : 21 - 21 (1 bit)

HTFIF5 : Half transfer finish flag of channel 5
bits : 22 - 22 (1 bit)

ERRIF5 : Error flag of channel 5
bits : 23 - 23 (1 bit)

GIF6 : Global interrupt flag of channel 6
bits : 24 - 24 (1 bit)

FTFIF6 : Full transfer finish flag of channel 6
bits : 25 - 25 (1 bit)

HTFIF6 : Half transfer finish flag of channel 6
bits : 26 - 26 (1 bit)

ERRIF6 : Error flag of channel 6
bits : 27 - 27 (1 bit)


CH0PADDR

DMA channel 0 peripheral base address register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0PADDR CH0PADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR

PADDR : Peripheral base address
bits : 0 - 31 (32 bit)


CH0MADDR

DMA channel 0 memory base address register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0MADDR CH0MADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory base address
bits : 0 - 31 (32 bit)


CH1CTL0

DMA channel configuration register (DMA_CH1CTL0)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CTL0 CH1CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN FTFIE HTFIE ERRIE DIR CMEN PNAGA MNAGA PWIDTH MWIDTH PRIO M2M

CHEN : Channel enable
bits : 0 - 0 (1 bit)

FTFIE : Enable bit for full transfer finish interrupt
bits : 1 - 1 (1 bit)

HTFIE : Enable bit for half transfer finish interrupt
bits : 2 - 2 (1 bit)

ERRIE : Enable bit for channel error interrupt
bits : 3 - 3 (1 bit)

DIR : Transfer direction
bits : 4 - 4 (1 bit)

CMEN : Circular mode enable
bits : 5 - 5 (1 bit)

PNAGA : Next address generation algorithm of peripheral
bits : 6 - 6 (1 bit)

MNAGA : Next address generation algorithm of memory
bits : 7 - 7 (1 bit)

PWIDTH : Transfer data size of peripheral
bits : 8 - 9 (2 bit)

MWIDTH : Transfer data size of memory
bits : 10 - 11 (2 bit)

PRIO : Priority Level of this channel
bits : 12 - 13 (2 bit)

M2M : Memory to memory mode
bits : 14 - 14 (1 bit)


CH1CNT

DMA channel 1 counter register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CNT CH1CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Transfer counter
bits : 0 - 15 (16 bit)


CH1PADDR

DMA channel 1 peripheral base address register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1PADDR CH1PADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR

PADDR : Peripheral base address
bits : 0 - 31 (32 bit)


CH1MADDR

DMA channel 1 memory base address register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1MADDR CH1MADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory base address
bits : 0 - 31 (32 bit)


CH2CTL0

DMA channel configuration register (DMA_CH2CTL0)
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2CTL0 CH2CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN FTFIE HTFIE ERRIE DIR CMEN PNAGA MNAGA PWIDTH MWIDTH PRIO M2M

CHEN : Channel enable
bits : 0 - 0 (1 bit)

FTFIE : Enable bit for full transfer finish interrupt
bits : 1 - 1 (1 bit)

HTFIE : Enable bit for half transfer finish interrupt
bits : 2 - 2 (1 bit)

ERRIE : Enable bit for channel error interrupt
bits : 3 - 3 (1 bit)

DIR : Transfer direction
bits : 4 - 4 (1 bit)

CMEN : Circular mode enable
bits : 5 - 5 (1 bit)

PNAGA : Next address generation algorithm of peripheral
bits : 6 - 6 (1 bit)

MNAGA : Next address generation algorithm of memory
bits : 7 - 7 (1 bit)

PWIDTH : Transfer data size of peripheral
bits : 8 - 9 (2 bit)

MWIDTH : Transfer data size of memory
bits : 10 - 11 (2 bit)

PRIO : Priority Level of this channel
bits : 12 - 13 (2 bit)

M2M : Memory to memory mode
bits : 14 - 14 (1 bit)


CH2CNT

DMA channel 2 counter register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2CNT CH2CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Transfer counter
bits : 0 - 15 (16 bit)


CH2PADDR

DMA channel 2 peripheral base address register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2PADDR CH2PADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR

PADDR : Peripheral base address
bits : 0 - 31 (32 bit)


CH2MADDR

DMA channel 2 memory base address register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2MADDR CH2MADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory base address
bits : 0 - 31 (32 bit)


INTC

DMA interrupt flag clear register (DMA_INTC)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INTC INTC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GIC0 FTFIFC0 HTFIFC0 ERRIFC0 GIC1 FTFIFC1 HTFIFC1 ERRIFC1 GIC2 FTFIFC2 HTFIFC2 ERRIFC2 GIC3 FTFIFC3 HTFIFC3 ERRIFC3 GIC4 FTFIFC4 HTFIFC4 ERRIFC4 GIC5 FTFIFC5 HTFIFC5 ERRIFC5 GIC6 FTFIFC6 HTFIFC6 ERRIFC6

GIC0 : Clear global interrupt flag of channel 0
bits : 0 - 0 (1 bit)

FTFIFC0 : Clear bit for Full transfer finish flag of channel 0
bits : 1 - 1 (1 bit)

HTFIFC0 : Clear bit for half transfer finish flag of channel 0
bits : 2 - 2 (1 bit)

ERRIFC0 : Clear bit for error flag of channel 0
bits : 3 - 3 (1 bit)

GIC1 : Clear global interrupt flag of channel 1
bits : 4 - 4 (1 bit)

FTFIFC1 : Clear bit for Full transfer finish flag of channel 1
bits : 5 - 5 (1 bit)

HTFIFC1 : Clear bit for half transfer finish flag of channel 1
bits : 6 - 6 (1 bit)

ERRIFC1 : Clear bit for error flag of channel 1
bits : 7 - 7 (1 bit)

GIC2 : Clear global interrupt flag of channel 2
bits : 8 - 8 (1 bit)

FTFIFC2 : Clear bit for Full transfer finish flag of channel 2
bits : 9 - 9 (1 bit)

HTFIFC2 : Clear bit for half transfer finish flag of channel 2
bits : 10 - 10 (1 bit)

ERRIFC2 : Clear bit for error flag of channel 2
bits : 11 - 11 (1 bit)

GIC3 : Clear global interrupt flag of channel 3
bits : 12 - 12 (1 bit)

FTFIFC3 : Clear bit for Full transfer finish flag of channel 3
bits : 13 - 13 (1 bit)

HTFIFC3 : Clear bit for half transfer finish flag of channel 3
bits : 14 - 14 (1 bit)

ERRIFC3 : Clear bit for error flag of channel 3
bits : 15 - 15 (1 bit)

GIC4 : Clear global interrupt flag of channel 4
bits : 16 - 16 (1 bit)

FTFIFC4 : Clear bit for Full transfer finish flag of channel 4
bits : 17 - 17 (1 bit)

HTFIFC4 : Clear bit for half transfer finish flag of channel 4
bits : 18 - 18 (1 bit)

ERRIFC4 : Clear bit for error flag of channel 4
bits : 19 - 19 (1 bit)

GIC5 : Clear global interrupt flag of channel 5
bits : 20 - 20 (1 bit)

FTFIFC5 : Clear bit for Full transfer finish flag of channel 5
bits : 21 - 21 (1 bit)

HTFIFC5 : Clear bit for half transfer finish flag of channel 5
bits : 22 - 22 (1 bit)

ERRIFC5 : Clear bit for error flag of channel 5
bits : 23 - 23 (1 bit)

GIC6 : Clear global interrupt flag of channel 6
bits : 24 - 24 (1 bit)

FTFIFC6 : Clear bit for Full transfer finish flag of channel 6
bits : 25 - 25 (1 bit)

HTFIFC6 : Clear bit for half transfer finish flag of channel 6
bits : 26 - 26 (1 bit)

ERRIFC6 : Clear bit for error flag of channel 6
bits : 27 - 27 (1 bit)


CH3CTL0

DMA channel configuration register (DMA_CH3CTL0)
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3CTL0 CH3CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN FTFIE HTFIE ERRIE DIR CMEN PNAGA MNAGA PWIDTH MWIDTH PRIO M2M

CHEN : Channel enable
bits : 0 - 0 (1 bit)

FTFIE : Enable bit for full transfer finish interrupt
bits : 1 - 1 (1 bit)

HTFIE : Enable bit for half transfer finish interrupt
bits : 2 - 2 (1 bit)

ERRIE : Enable bit for channel error interrupt
bits : 3 - 3 (1 bit)

DIR : Transfer direction
bits : 4 - 4 (1 bit)

CMEN : Circular mode enable
bits : 5 - 5 (1 bit)

PNAGA : Next address generation algorithm of peripheral
bits : 6 - 6 (1 bit)

MNAGA : Next address generation algorithm of memory
bits : 7 - 7 (1 bit)

PWIDTH : Transfer data size of peripheral
bits : 8 - 9 (2 bit)

MWIDTH : Transfer data size of memory
bits : 10 - 11 (2 bit)

PRIO : Priority Level of this channel
bits : 12 - 13 (2 bit)

M2M : Memory to memory mode
bits : 14 - 14 (1 bit)


CH3CNT

DMA channel 3 counter register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3CNT CH3CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Transfer counter
bits : 0 - 15 (16 bit)


CH3PADDR

DMA channel 3 peripheral base address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3PADDR CH3PADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR

PADDR : Peripheral base address
bits : 0 - 31 (32 bit)


CH3MADDR

DMA channel 3 memory base address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3MADDR CH3MADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory base address
bits : 0 - 31 (32 bit)


CH4CTL0

DMA channel configuration register (DMA_CH4CTL0)
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4CTL0 CH4CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN FTFIE HTFIE ERRIE DIR CMEN PNAGA MNAGA PWIDTH MWIDTH PRIO M2M

CHEN : Channel enable
bits : 0 - 0 (1 bit)

FTFIE : Enable bit for full transfer finish interrupt
bits : 1 - 1 (1 bit)

HTFIE : Enable bit for half transfer finish interrupt
bits : 2 - 2 (1 bit)

ERRIE : Enable bit for channel error interrupt
bits : 3 - 3 (1 bit)

DIR : Transfer direction
bits : 4 - 4 (1 bit)

CMEN : Circular mode enable
bits : 5 - 5 (1 bit)

PNAGA : Next address generation algorithm of peripheral
bits : 6 - 6 (1 bit)

MNAGA : Next address generation algorithm of memory
bits : 7 - 7 (1 bit)

PWIDTH : Transfer data size of peripheral
bits : 8 - 9 (2 bit)

MWIDTH : Transfer data size of memory
bits : 10 - 11 (2 bit)

PRIO : Priority Level of this channel
bits : 12 - 13 (2 bit)

M2M : Memory to memory mode
bits : 14 - 14 (1 bit)


CH4CNT

DMA channel 4 counter register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4CNT CH4CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Transfer counter
bits : 0 - 15 (16 bit)


CH4PADDR

DMA channel 4 peripheral base address register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4PADDR CH4PADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR

PADDR : Peripheral base address
bits : 0 - 31 (32 bit)


CH4MADDR

DMA channel 4 memory base address register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4MADDR CH4MADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory base address
bits : 0 - 31 (32 bit)


CH5CTL0

DMA channel configuration register (DMA_CH5CTL0)
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5CTL0 CH5CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN FTFIE HTFIE ERRIE DIR CMEN PNAGA MNAGA PWIDTH MWIDTH PRIO M2M

CHEN : Channel enable
bits : 0 - 0 (1 bit)

FTFIE : Enable bit for full transfer finish interrupt
bits : 1 - 1 (1 bit)

HTFIE : Enable bit for half transfer finish interrupt
bits : 2 - 2 (1 bit)

ERRIE : Enable bit for channel error interrupt
bits : 3 - 3 (1 bit)

DIR : Transfer direction
bits : 4 - 4 (1 bit)

CMEN : Circular mode enable
bits : 5 - 5 (1 bit)

PNAGA : Next address generation algorithm of peripheral
bits : 6 - 6 (1 bit)

MNAGA : Next address generation algorithm of memory
bits : 7 - 7 (1 bit)

PWIDTH : Transfer data size of peripheral
bits : 8 - 9 (2 bit)

MWIDTH : Transfer data size of memory
bits : 10 - 11 (2 bit)

PRIO : Priority Level of this channel
bits : 12 - 13 (2 bit)

M2M : Memory to memory mode
bits : 14 - 14 (1 bit)


CH5CNT

DMA channel 5 counter register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5CNT CH5CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Transfer counter
bits : 0 - 15 (16 bit)


CH5PADDR

DMA channel 5 peripheral base address register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5PADDR CH5PADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR

PADDR : Peripheral base address
bits : 0 - 31 (32 bit)


CH5MADDR

DMA channel 5 memory base address register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5MADDR CH5MADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory base address
bits : 0 - 31 (32 bit)


CH0CTL0

DMA channel configuration register (DMA_CH0CTL0)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0CTL0 CH0CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN FTFIE HTFIE ERRIE DIR CMEN PNAGA MNAGA PWIDTH MWIDTH PRIO M2M

CHEN : Channel enable
bits : 0 - 0 (1 bit)

FTFIE : Enable bit for full transfer finish interrupt
bits : 1 - 1 (1 bit)

HTFIE : Enable bit for half transfer finish interrupt
bits : 2 - 2 (1 bit)

ERRIE : Enable bit for channel error interrupt
bits : 3 - 3 (1 bit)

DIR : Transfer direction
bits : 4 - 4 (1 bit)

CMEN : Circular mode enable
bits : 5 - 5 (1 bit)

PNAGA : Next address generation algorithm of peripheral
bits : 6 - 6 (1 bit)

MNAGA : Next address generation algorithm of memory
bits : 7 - 7 (1 bit)

PWIDTH : Transfer data size of peripheral
bits : 8 - 9 (2 bit)

MWIDTH : Transfer data size of memory
bits : 10 - 11 (2 bit)

PRIO : Priority Level of this channel
bits : 12 - 13 (2 bit)

M2M : Memory to memory mode
bits : 14 - 14 (1 bit)


CH6CTL0

DMA channel configuration register (DMA_CH6CTL0)
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6CTL0 CH6CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN FTFIE HTFIE ERRIE DIR CMEN PNAGA MNAGA PWIDTH MWIDTH PRIO M2M

CHEN : Channel enable
bits : 0 - 0 (1 bit)

FTFIE : Enable bit for full transfer finish interrupt
bits : 1 - 1 (1 bit)

HTFIE : Enable bit for full transfer finish interrupt
bits : 2 - 2 (1 bit)

ERRIE : Enable bit for channel error interrupt
bits : 3 - 3 (1 bit)

DIR : Transfer direction
bits : 4 - 4 (1 bit)

CMEN : Circular mode enable
bits : 5 - 5 (1 bit)

PNAGA : Next address generation algorithm of peripheral
bits : 6 - 6 (1 bit)

MNAGA : Next address generation algorithm of memory
bits : 7 - 7 (1 bit)

PWIDTH : Transfer data size of peripheral
bits : 8 - 9 (2 bit)

MWIDTH : Transfer data size of memory
bits : 10 - 11 (2 bit)

PRIO : Priority Level of this channel
bits : 12 - 13 (2 bit)

M2M : Memory to memory mode
bits : 14 - 14 (1 bit)


CH6CNT

DMA channel 6 counter register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6CNT CH6CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Transfer counter
bits : 0 - 15 (16 bit)


CH6PADDR

DMA channel 6 peripheral base address register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6PADDR CH6PADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR

PADDR : Peripheral base address
bits : 0 - 31 (32 bit)


CH6MADDR

DMA channel 6 memory base address register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6MADDR CH6MADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory base address
bits : 0 - 31 (32 bit)


CH0CNT

DMA channel 0 counter register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0CNT CH0CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Transfer counter
bits : 0 - 15 (16 bit)



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