\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2CEN : I2C peripheral enable
bits : 0 - 0 (1 bit)
SMBEN : SMBus/I2C mode switch
bits : 1 - 1 (1 bit)
SMBSEL : SMBusType Selection
bits : 3 - 3 (1 bit)
ARPEN : ARP protocol in SMBus switch
bits : 4 - 4 (1 bit)
PECEN : PEC Calculation Switch
bits : 5 - 5 (1 bit)
GCEN : Whether or not to response to a General Call (0x00)
bits : 6 - 6 (1 bit)
SS : Whether to stretch SCL low when data is not ready in slave mode
bits : 7 - 7 (1 bit)
START : Generate a START condition on I2C bus
bits : 8 - 8 (1 bit)
STOP : Generate a STOP condition on I2C bus
bits : 9 - 9 (1 bit)
ACKEN : Whether or not to send an ACK
bits : 10 - 10 (1 bit)
POAP : Position of ACK meaning
bits : 11 - 11 (1 bit)
PECTRANS : PEC Transfer
bits : 12 - 12 (1 bit)
SALT : SMBus alert
bits : 13 - 13 (1 bit)
SRESET : Software reset I2C
bits : 15 - 15 (1 bit)
Data register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRB : Transmission or reception data buffer register
bits : 0 - 7 (8 bit)
Transfer status register 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBSEND : START condition sent out in master mode
bits : 0 - 0 (1 bit)
access : read-only
ADDSEND : Address is sent in master mode or received and matches in slave mode
bits : 1 - 1 (1 bit)
access : read-only
BTC : Byte transmission completed
bits : 2 - 2 (1 bit)
access : read-only
ADD10SEND : Header of 10-bit address is sent in master mode
bits : 3 - 3 (1 bit)
access : read-only
STPDET : STOP condition detected in slave mode
bits : 4 - 4 (1 bit)
access : read-only
RBNE : TRBR is not Empty during receiving
bits : 6 - 6 (1 bit)
access : read-only
TBE : I2C_DATA is Empty during transmitting
bits : 7 - 7 (1 bit)
access : read-only
BERR : Bus error
bits : 8 - 8 (1 bit)
access : read-write
LOSTARB : Arbitration Lost in master mode
bits : 9 - 9 (1 bit)
access : read-write
AERR : Acknowledge error
bits : 10 - 10 (1 bit)
access : read-write
OUERR : Over-run or under-run situation occurs in slave mode
bits : 11 - 11 (1 bit)
access : read-write
PECERR : PEC error when receiving data
bits : 12 - 12 (1 bit)
access : read-write
SMBTO : Timeout signal in SMBus mode
bits : 14 - 14 (1 bit)
access : read-write
SMBALTS : SMBus Alert status
bits : 15 - 15 (1 bit)
access : read-write
Transfer status register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MASTER : A flag indicating whether I2C block is in master or slave mode
bits : 0 - 0 (1 bit)
I2CBSY : Busy flag
bits : 1 - 1 (1 bit)
TR : Whether the I2C is a transmitter or a receiver
bits : 2 - 2 (1 bit)
RXGC : General call address (00h) received
bits : 4 - 4 (1 bit)
DEFSMB : SMBus host header in slave mode
bits : 5 - 5 (1 bit)
HSTSMB : SMBus Host Header detected in slave mode
bits : 6 - 6 (1 bit)
DUMODF : Dual Flag in slave mode
bits : 7 - 7 (1 bit)
PECV : Packet Error Checking Value
bits : 8 - 15 (8 bit)
Clock configure register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKC : I2C Clock control in master mode
bits : 0 - 11 (12 bit)
DTCY : Duty cycle in fast mode
bits : 14 - 14 (1 bit)
FAST : I2C speed selection in master mode
bits : 15 - 15 (1 bit)
Rise time register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RISETIME : Maximum rise time in master mode
bits : 0 - 6 (7 bit)
Control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2CCLK : I2C Peripheral clock frequency
bits : 0 - 6 (7 bit)
ERRIE : Error interrupt enable
bits : 8 - 8 (1 bit)
EVIE : Event interrupt enable
bits : 9 - 9 (1 bit)
BUFIE : Buffer interrupt enable
bits : 10 - 10 (1 bit)
DMAON : DMA mode switch
bits : 11 - 11 (1 bit)
DMALST : Flag indicating DMA last transfer
bits : 12 - 12 (1 bit)
Own address register 0
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Interface address
bits : 0 - 9 (10 bit)
ADDFORMAT : Address mode for the I2C slave
bits : 15 - 15 (1 bit)
SAM Controland status register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAMEN : SAM_V interface enable
bits : 0 - 0 (1 bit)
STOEN : SAM_V interface timeout detect enable
bits : 1 - 1 (1 bit)
TFFIE : Txframe fall interrupt enable
bits : 4 - 4 (1 bit)
TFRIE : Txframe rise interrupt enable
bits : 5 - 5 (1 bit)
RFFIE : Rxframe fall interrupt enable
bits : 6 - 6 (1 bit)
RFRIE : Rxframe rise interrupt enable
bits : 7 - 7 (1 bit)
TXF : Level of Txframe signal
bits : 8 - 8 (1 bit)
RXF : Level of Rxframe signal
bits : 9 - 9 (1 bit)
TFF : Txframe fall flag
bits : 12 - 12 (1 bit)
TFR : Txframe rise flag
bits : 13 - 13 (1 bit)
RFF : Rxframe fall flag
bits : 14 - 14 (1 bit)
RFR : Rxframe rise flag
bits : 15 - 15 (1 bit)
Own address register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUADEN : Dual-Address mode switch
bits : 0 - 0 (1 bit)
ADDRESS2 : Second I2C address for the slave in Dual-Address mode
bits : 1 - 7 (7 bit)
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