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OPA_IVREF

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

IVREF_CTL

OPA_CTL

OPA_BT

OPA_LPBT


IVREF_CTL

IVREF control register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IVREF_CTL IVREF_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSDT SCMOD CPT SSEL CREN VPT DECAP VREN

CSDT : Current step data
bits : 0 - 5 (6 bit)
access : read-write

SCMOD : Sink current mode
bits : 7 - 7 (1 bit)
access : read-write

CPT : Current precision trim
bits : 8 - 12 (5 bit)
access : read-write

SSEL : Step selection
bits : 14 - 14 (1 bit)
access : read-write

CREN : Current reference enable
bits : 15 - 15 (1 bit)
access : read-write

VPT : Voltage precision tirm
bits : 24 - 28 (5 bit)
access : read-write

DECAP : Disconnect external capacitor
bits : 30 - 30 (1 bit)
access : read-write

VREN : Voltage reference enable
bits : 31 - 31 (1 bit)
access : read-write


OPA_CTL

OPA control register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA_CTL OPA_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPA0PD T3OPA0 S1OPA0 S2OPA0 S3OPA0 OPA0CAL_L OPA0CAL_H OPA0LPM OPA1PD T3OPA1 S1OPA1 S2OPA1 S3OPA1 OPA1CAL_L OPA1CAL_H OPA1LPM OPA2PD T3OPA2 S1OPA2 S2OPA2 S3OPA2 OPA2CAL_L OPA2CAL_H OPA2LPM S4OPA1 OPA_RANGE OPA0CALOUT OPA1CALOUT OPA2CALOUT

OPA0PD : OPA0 power down
bits : 0 - 0 (1 bit)
access : read-write

T3OPA0 : T3 switch enable for OPA0
bits : 1 - 1 (1 bit)
access : read-write

S1OPA0 : S1 switch enable for OPA0
bits : 2 - 2 (1 bit)
access : read-write

S2OPA0 : S2 switch enable for OPA0
bits : 3 - 3 (1 bit)
access : read-write

S3OPA0 : S3 switch enable for OPA0
bits : 4 - 4 (1 bit)
access : read-write

OPA0CAL_L : OPA0 offset calibration for P diff
bits : 5 - 5 (1 bit)
access : read-write

OPA0CAL_H : OPA0 offset calibration for N diff
bits : 6 - 6 (1 bit)
access : read-write

OPA0LPM : OPA0 low power mode
bits : 7 - 7 (1 bit)
access : read-write

OPA1PD : OPA1 power down
bits : 8 - 8 (1 bit)
access : read-write

T3OPA1 : T3 switch enable for OPA1
bits : 9 - 9 (1 bit)
access : read-write

S1OPA1 : S1 switch enable for OPA1
bits : 10 - 10 (1 bit)
access : read-write

S2OPA1 : S2 switch enable for OPA1
bits : 11 - 11 (1 bit)
access : read-write

S3OPA1 : S3 switch enable for OPA1
bits : 12 - 12 (1 bit)
access : read-write

OPA1CAL_L : OPA1 offset calibration for P diff
bits : 13 - 13 (1 bit)
access : read-write

OPA1CAL_H : OPA1 offset calibration for N diff
bits : 14 - 14 (1 bit)
access : read-write

OPA1LPM : OPA1 low power mode
bits : 15 - 15 (1 bit)
access : read-write

OPA2PD : OPA2 power down
bits : 16 - 16 (1 bit)
access : read-write

T3OPA2 : T3 switch enable for OPA2
bits : 17 - 17 (1 bit)
access : read-write

S1OPA2 : S1 switch enable for OPA2
bits : 18 - 18 (1 bit)
access : read-write

S2OPA2 : S2 switch enable for OPA2
bits : 19 - 19 (1 bit)
access : read-write

S3OPA2 : S3 switch enable for OPA2
bits : 20 - 20 (1 bit)
access : read-write

OPA2CAL_L : OPA2 offset calibration for P diff
bits : 21 - 21 (1 bit)
access : read-write

OPA2CAL_H : OPA2 offset calibration for N diff
bits : 22 - 22 (1 bit)
access : read-write

OPA2LPM : OPA2 low power mode
bits : 23 - 23 (1 bit)
access : read-write

S4OPA1 : S4 switch enable for OPA1
bits : 27 - 27 (1 bit)
access : read-write

OPA_RANGE : Power supply range
bits : 28 - 28 (1 bit)
access : read-write

OPA0CALOUT : OPA0 calibration output
bits : 29 - 29 (1 bit)
access : read-only

OPA1CALOUT : OPA1 calibration output
bits : 30 - 30 (1 bit)
access : read-only

OPA2CALOUT : OPA2 calibration output
bits : 31 - 31 (1 bit)
access : read-only


OPA_BT

OPA offset trimming for normal mode register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA_BT OPA_BT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OA0_TRIM_LOW OA0_TRIM_HIGH OA1_TRIM_LOW OA1_TRIM_HIGH OA2_TRIM_LOW OA2_TRIM_HIGH OT_USER

OA0_TRIM_LOW : OPA0, normal mode 5-bit offset trim value for PMOS pairs
bits : 0 - 4 (5 bit)
access : read-write

OA0_TRIM_HIGH : OPA0, normal mode 5-bit offset trim value for NMOS pairs
bits : 5 - 9 (5 bit)
access : read-write

OA1_TRIM_LOW : OPA1, normal mode 5-bit offset trim value for PMOS pairs
bits : 10 - 14 (5 bit)
access : read-write

OA1_TRIM_HIGH : OPA1, normal mode 5-bit offset trim value for NMOS pairs
bits : 15 - 19 (5 bit)
access : read-write

OA2_TRIM_LOW : OPA2, normal mode 5-bit offset trim value for PMOS pairs
bits : 20 - 24 (5 bit)
access : read-write

OA2_TRIM_HIGH : OPA2, normal mode 5-bit offset trim value for NMOS pairs
bits : 25 - 29 (5 bit)
access : read-write

OT_USER : user programmed trimming value
bits : 31 - 31 (1 bit)
access : write-only


OPA_LPBT

OPA offset trimming for low power mode register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA_LPBT OPA_LPBT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OA0_TRIM_LP_LOW OA0_TRIM_LP_HIGH OA1_TRIM_LP_LOW OA1_TRIM_LP_HIGH OA2_TRIM_LP_LOW OA2_TRIM_LP_HIGH

OA0_TRIM_LP_LOW : OPA0, low power mode 5-bit offset trim value for PMOS pairs
bits : 0 - 4 (5 bit)
access : read-write

OA0_TRIM_LP_HIGH : OPA0, low power mode 5-bit offset trim value for NMOS pairs
bits : 5 - 9 (5 bit)
access : read-write

OA1_TRIM_LP_LOW : OPA1, low power mode 5-bit offset trim value for PMOS pairs
bits : 10 - 14 (5 bit)
access : read-write

OA1_TRIM_LP_HIGH : OPA1, low power mode 5-bit offset trim value for NMOS pairs
bits : 15 - 19 (5 bit)
access : read-write

OA2_TRIM_LP_LOW : OPA2, low power mode 5-bit offset trim value for PMOS pairs
bits : 20 - 24 (5 bit)
access : read-write

OA2_TRIM_LP_HIGH : OPA2, low power mode 5-bit offset trim value for NMOS pairs
bits : 25 - 29 (5 bit)
access : read-write



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