\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRC8MEN : Internal High Speed oscillator Enable
bits : 0 - 0 (1 bit)
access : read-write
IRC8MSTB : IRC8M High Speed Internal Oscillator stabilization Flag
bits : 1 - 1 (1 bit)
access : read-only
IRC8MADJ : High Speed Internal Oscillator clock trim adjust value
bits : 3 - 7 (5 bit)
access : read-write
IRC8MCALIB : High Speed Internal Oscillator calibration value register
bits : 8 - 15 (8 bit)
access : read-only
HXTALEN : External High Speed oscillator Enable
bits : 16 - 16 (1 bit)
access : read-write
HXTALSTB : External crystal oscillator (HXTAL) clock stabilization flag
bits : 17 - 17 (1 bit)
access : read-only
HXTALBPS : External crystal oscillator (HXTAL) clock bypass mode enable
bits : 18 - 18 (1 bit)
access : read-write
CKMEN : HXTAL Clock Monitor Enable
bits : 19 - 19 (1 bit)
access : read-write
PLLEN : PLL enable
bits : 24 - 24 (1 bit)
access : read-write
PLLSTB : PLL Clock Stabilization Flag
bits : 25 - 25 (1 bit)
access : read-only
APB1 reset register (RCU_APB1RST)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMER1RST : TIMER1 timer reset
bits : 0 - 0 (1 bit)
TIMER2RST : TIMER2 timer reset
bits : 1 - 1 (1 bit)
TIMER5RST : TIMER5 timer reset
bits : 4 - 4 (1 bit)
TIMER13RST : TIMER13 timer reset
bits : 8 - 8 (1 bit)
SLCDRST : SLCD reset
bits : 9 - 9 (1 bit)
WWDGTRST : Window watchdog timer reset
bits : 11 - 11 (1 bit)
SPI1RST : SPI1 reset
bits : 14 - 14 (1 bit)
SPI2RST : SPI2 reset
bits : 15 - 15 (1 bit)
USART1RST : USART1 reset
bits : 17 - 17 (1 bit)
I2C0RST : I2C0 reset
bits : 21 - 21 (1 bit)
I2C1RST : I2C1 reset
bits : 22 - 22 (1 bit)
USBDRST : USBD reset
bits : 23 - 23 (1 bit)
CAN0RST : CAN0 reset
bits : 25 - 25 (1 bit)
CAN1RST : CAN1 reset
bits : 26 - 26 (1 bit)
PMURST : Power control reset
bits : 28 - 28 (1 bit)
DACRST : DAC reset
bits : 29 - 29 (1 bit)
CECRST : HDMI CEC reset
bits : 30 - 30 (1 bit)
OPAIVREFRST : OPA and IVREF reset
bits : 31 - 31 (1 bit)
Voltage key register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : The key of RCU_PDVSEL and RCU_DSV register
bits : 0 - 31 (32 bit)
access : write-only
Deep-sleep mode voltage register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSLPVS : Deep-sleep mode voltage select
bits : 0 - 2 (3 bit)
access : read-write
Power down voltage select register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDRVS : Power down voltage select
bits : 0 - 0 (1 bit)
access : read-write
AHB enable register (RCU_AHBEN)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : DMA clock enable
bits : 0 - 0 (1 bit)
SRAMSPEN : SRAM interface clock enable
bits : 2 - 2 (1 bit)
FMCSPEN : FMC clock enable
bits : 4 - 4 (1 bit)
CRCEN : CRC clock enable
bits : 6 - 6 (1 bit)
PAEN : GPIO port A clock enable
bits : 17 - 17 (1 bit)
PBEN : GPIO port B clock enable
bits : 18 - 18 (1 bit)
PCEN : GPIO port C clock enable
bits : 19 - 19 (1 bit)
PDEN : GPIO port D clock enable
bits : 20 - 20 (1 bit)
PFEN : GPIO port F clock enable
bits : 22 - 22 (1 bit)
TSIEN : TSI clock enable
bits : 24 - 24 (1 bit)
APB2 enable register (RCU_APB2EN)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGCMPEN : System configuration and comparator clock enable
bits : 0 - 0 (1 bit)
ADCEN : ADC interface clock enable
bits : 9 - 9 (1 bit)
TIMER0EN : TIMER0 timer clock enable
bits : 11 - 11 (1 bit)
SPI0EN : SPI0 clock enable
bits : 12 - 12 (1 bit)
USART0EN : USART0 clock enable
bits : 14 - 14 (1 bit)
TIMER14EN : TIMER14 timer clock enable
bits : 16 - 16 (1 bit)
TIMER15EN : TIMER15 timer clock enable
bits : 17 - 17 (1 bit)
TIMER16EN : TIMER16 timer clock enable
bits : 18 - 18 (1 bit)
APB1 enable register (RCU_APB1EN)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMER1EN : TIMER1 timer clock enable
bits : 0 - 0 (1 bit)
TIMER2EN : TIMER2 timer clock enable
bits : 1 - 1 (1 bit)
TIMER5EN : TIMER5 timer clock enable
bits : 4 - 4 (1 bit)
TIMER13EN : TIMER13 timer clock enable
bits : 8 - 8 (1 bit)
SLCDEN : SLCD clock enable
bits : 9 - 9 (1 bit)
WWDGTEN : Window watchdog timer clock enable
bits : 11 - 11 (1 bit)
SPI1EN : SPI1 clock enable
bits : 14 - 14 (1 bit)
SPI2EN : SPI2 clock enable
bits : 15 - 15 (1 bit)
USART1EN : USART1 clock enable
bits : 17 - 17 (1 bit)
I2C0EN : I2C0 clock enable
bits : 21 - 21 (1 bit)
I2C1EN : I2C1 clock enable
bits : 22 - 22 (1 bit)
USBDEN : USBD clock enable
bits : 23 - 23 (1 bit)
CAN0EN : CAN0 clock enable
bits : 25 - 25 (1 bit)
CAN1EN : CAN1 clock enable
bits : 26 - 26 (1 bit)
PMUEN : Power interface clock enable
bits : 28 - 28 (1 bit)
DACEN : DAC interface clock enable
bits : 29 - 29 (1 bit)
CECEN : HDMI CEC interface clock enable
bits : 30 - 30 (1 bit)
OPAIVREFEN : OPA and IVREF clock enable
bits : 31 - 31 (1 bit)
Backup domain control register (RCU_BDCTL)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LXTALEN : LXTAL enable
bits : 0 - 0 (1 bit)
access : read-write
LXTALSTB : External low-speed oscillator stabilization
bits : 1 - 1 (1 bit)
access : read-only
LXTALBPS : LXTAL bypass mode enable
bits : 2 - 2 (1 bit)
access : read-write
LXTALDRI : LXTAL drive capability
bits : 3 - 4 (2 bit)
access : read-write
RTCSRC : RTC clock entry selection
bits : 8 - 9 (2 bit)
access : read-write
RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)
access : read-write
BKPRST : Backup domain reset
bits : 16 - 16 (1 bit)
access : read-write
Reset source /clock register (RCU_RSTSCK)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRC40KEN : IRC40K enable
bits : 0 - 0 (1 bit)
access : read-write
IRC40KSTB : IRC40K stabilization
bits : 1 - 1 (1 bit)
access : read-only
V12RSTF : V12 domain Power reset flag
bits : 23 - 23 (1 bit)
access : read-write
RSTFC : Reset flag clear
bits : 24 - 24 (1 bit)
access : read-write
OBLRSTF : Option byte loader reset flag
bits : 25 - 25 (1 bit)
access : read-write
EPRSTF : External PIN reset flag
bits : 26 - 26 (1 bit)
access : read-write
PORRSTF : Power reset flag
bits : 27 - 27 (1 bit)
access : read-write
SWRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-write
FWDGTRSTF : Free Watchdog timer reset flag
bits : 29 - 29 (1 bit)
access : read-write
WWDGTRSTF : Window watchdog timer reset flag
bits : 30 - 30 (1 bit)
access : read-write
LPRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
access : read-write
AHB reset register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARST : GPIO port A reset
bits : 17 - 17 (1 bit)
PBRST : GPIO port B reset
bits : 18 - 18 (1 bit)
PCRST : GPIO port C reset
bits : 19 - 19 (1 bit)
PDRST : GPIO port D reset
bits : 20 - 20 (1 bit)
PFRST : GPIO port F reset
bits : 22 - 22 (1 bit)
TSIRST : TSI unit reset
bits : 24 - 24 (1 bit)
Configuration register 1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTALPREDV : CK_HXTAL divider previous PLL
bits : 0 - 3 (4 bit)
Configuration register 2
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USART0SEL : CK_USART0 clock source selection
bits : 0 - 1 (2 bit)
CECSEL : CK_CEC clock source selection
bits : 6 - 6 (1 bit)
ADCSEL : CK_ADC clock source selection
bits : 8 - 8 (1 bit)
IRC28MDIV : CK_IRC28M divider 2 or not
bits : 16 - 16 (1 bit)
Control register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRC14MEN : IRC14M Internal 14M RC oscillator Enable
bits : 0 - 0 (1 bit)
access : read-write
IRC14MSTB : IRC14M Internal 14M RC Oscillator stabilization Flag
bits : 1 - 1 (1 bit)
access : read-only
IRC14MADJ : Internal 14M RC Oscillator clock trim adjust value
bits : 3 - 7 (5 bit)
access : read-write
IRC14MCALIB : Internal 14M RC Oscillator calibration value register
bits : 8 - 15 (8 bit)
access : read-only
Clock configuration register 0 (RCU_CFG0)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCS : System clock switch
bits : 0 - 1 (2 bit)
access : read-write
SCSS : System clock switch status
bits : 2 - 3 (2 bit)
access : read-only
AHBPSC : AHB prescaler selection
bits : 4 - 7 (4 bit)
access : read-write
APB1PSC : APB1 prescaler selection
bits : 8 - 10 (3 bit)
access : read-write
APB2PSC : APB2 prescaler selection
bits : 11 - 13 (3 bit)
access : read-write
ADCPSC : ADC clock prescaler selection
bits : 14 - 15 (2 bit)
access : read-write
PLLSEL : PLL Clock Source Selection
bits : 16 - 16 (1 bit)
access : read-write
PLLPREDV : HXTAL divider for PLL source clock selection.
bits : 17 - 17 (1 bit)
access : read-write
PLLMF : PLL multiply factor
bits : 18 - 21 (4 bit)
access : read-write
USBDPSC : USBD clock prescaler selection
bits : 22 - 23 (2 bit)
access : read-write
CKOUTSEL : CK_OUT Clock Source Selection
bits : 24 - 26 (3 bit)
access : read-write
PLLMF_MSB : Bit 4 of PLLMF register
bits : 27 - 27 (1 bit)
access : read-write
CKOUTDIV : The CK_OUT divider which the CK_OUT frequency can be reduced
bits : 28 - 30 (3 bit)
access : read-write
PLLDV : The CK_PLL divide by 1 or 2 for CK_OUT
bits : 31 - 31 (1 bit)
access : read-write
Clock interrupt register (RCU_INT)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRC40KSTBIF : IRC40K stabilization interrupt flag
bits : 0 - 0 (1 bit)
access : read-only
LXTALSTBIF : LXTAL stabilization interrupt flag
bits : 1 - 1 (1 bit)
access : read-only
IRC8MSTBIF : IRC8M stabilization interrupt flag
bits : 2 - 2 (1 bit)
access : read-only
HXTALSTBIF : HXTAL stabilization interrupt flag
bits : 3 - 3 (1 bit)
access : read-only
PLLSTBIF : PLL stabilization interrupt flag
bits : 4 - 4 (1 bit)
access : read-only
IRC14MSTBIF : IRC14M stabilization interrupt flag
bits : 5 - 5 (1 bit)
access : read-only
CKMIF : HXTAL Clock Stuck Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-only
IRC40KSTBIE : IRC40K Stabilization interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
LXTALSTBIE : LXTAL Stabilization Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
IRC8MSTBIE : IRC8M Stabilization Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
HXTALSTBIE : HXTAL Stabilization Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
PLLSTBIE : PLL Stabilization Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
IRC14MSTBIE : IRC14M Stabilization Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
IRC40KSTBIC : IRC40K Stabilization Interrupt Clear
bits : 16 - 16 (1 bit)
access : write-only
LXTALSTBIC : LXTAL Stabilization Interrupt Clear
bits : 17 - 17 (1 bit)
access : write-only
IRC8MSTBIC : IRC8M Stabilization Interrupt Clear
bits : 18 - 18 (1 bit)
access : write-only
HXTALSTBIC : HXTAL Stabilization Interrupt Clear
bits : 19 - 19 (1 bit)
access : write-only
PLLSTBIC : PLL stabilization Interrupt Clear
bits : 20 - 20 (1 bit)
access : write-only
IRC14MSTBIC : IRC14M stabilization Interrupt Clear
bits : 21 - 21 (1 bit)
access : write-only
CKMIC : HXTAL Clock Stuck Interrupt Clear
bits : 23 - 23 (1 bit)
access : write-only
Configuration register 4
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKOUT1SEL : CKOUT1 Clock Source Selection
bits : 0 - 2 (3 bit)
access : read-write
CKOUT1DIV : The CK_OUT1 divider which the CK_OUT1 frequency can be reduced see bits 2:0 of RCU_CFG3 for CK_OUT1
bits : 8 - 13 (6 bit)
access : read-write
APB2 reset register (RCU_APB2RST)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGCMPRST : System configuration and comparator reset
bits : 0 - 0 (1 bit)
ADCRST : ADC reset
bits : 9 - 9 (1 bit)
TIMER0RST : TIMER0 reset
bits : 11 - 11 (1 bit)
SPI0RST : SPI0 Reset
bits : 12 - 12 (1 bit)
USART0RST : USART0 Reset
bits : 14 - 14 (1 bit)
TIMER14RST : TIMER14 reset
bits : 16 - 16 (1 bit)
TIMER15RST : TIMER15 reset
bits : 17 - 17 (1 bit)
TIMER16RST : TIMER16 reset
bits : 18 - 18 (1 bit)
Additional enable register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C2EN : I2C2 unit clock enable
bits : 0 - 0 (1 bit)
access : read-write
Additional reset register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C2RST : I2C2 unit reset
bits : 0 - 0 (1 bit)
access : read-write
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