RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

add a new register to this peripheral

TIME

PSC

ALRM0TD

WPK

SS

SHIFTCTL

TTS

DTS

SSTS

HRFC

DATE

TAMP

ALRM0SS

BKP0

BKP1

BKP2

BKP3

BKP4

CTL

STAT


TIME

Time of day register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIME TIME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCU SCT MNU MNT HRU HRT PM

SCU : Second units in BCD format
bits : 0 - 3 (4 bit)

SCT : Second tens in BCD format
bits : 4 - 6 (3 bit)

MNU : Minute units in BCD format
bits : 8 - 11 (4 bit)

MNT : Minute tens in BCD format
bits : 12 - 14 (3 bit)

HRU : Hour units in BCD format
bits : 16 - 19 (4 bit)

HRT : Hour tens in BCD format
bits : 20 - 21 (2 bit)

PM : AM/PM mark
bits : 22 - 22 (1 bit)


PSC

Time prescaler register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSC PSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FACTOR_S FACTOR_A

FACTOR_S : Synchronous prescaler factor
bits : 0 - 14 (15 bit)

FACTOR_A : Asynchronous prescaler factor
bits : 16 - 22 (7 bit)


ALRM0TD

Alarm 0 Time and date register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALRM0TD ALRM0TD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCU SCT MSKS MNU MNT MSKM HRU HRT PM MSKH DAYU DAYT DOWS MSKD

SCU : Second units in BCD code
bits : 0 - 3 (4 bit)

SCT : Second tens in BCD code
bits : 4 - 6 (3 bit)

MSKS : Alarm second mask bit
bits : 7 - 7 (1 bit)

MNU : Minutes units in BCD code
bits : 8 - 11 (4 bit)

MNT : Minutes tens in BCD code
bits : 12 - 14 (3 bit)

MSKM : Alarm minutes mask bit
bits : 15 - 15 (1 bit)

HRU : Hour units in BCD code
bits : 16 - 19 (4 bit)

HRT : Hour tens in BCD code
bits : 20 - 21 (2 bit)

PM : AM/PM flag
bits : 22 - 22 (1 bit)

MSKH : Alarm hour mask bit
bits : 23 - 23 (1 bit)

DAYU : Date units or week day in BCD code
bits : 24 - 27 (4 bit)

DAYT : Date tens in BCD code
bits : 28 - 29 (2 bit)

DOWS : Day of the week selected
bits : 30 - 30 (1 bit)

MSKD : Alarm date mask bit
bits : 31 - 31 (1 bit)


WPK

Write protection key register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

WPK WPK write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPK

WPK : Write protection key
bits : 0 - 7 (8 bit)


SS

sub second register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SS SS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSC

SSC : Sub second value
bits : 0 - 15 (16 bit)


SHIFTCTL

Shift function control register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SHIFTCTL SHIFTCTL write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFS A1S

SFS : Subtract a fraction of a second
bits : 0 - 14 (15 bit)

A1S : One second add
bits : 31 - 31 (1 bit)


TTS

Time of time stamp register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TTS TTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCU SCT MNU MNT HRU HRT PM

SCU : Second units in BCD code
bits : 0 - 3 (4 bit)

SCT : Second tens in BCD code
bits : 4 - 6 (3 bit)

MNU : Minute units in BCD code
bits : 8 - 11 (4 bit)

MNT : Minute tens in BCD code
bits : 12 - 14 (3 bit)

HRU : Hour units in BCD code
bits : 16 - 19 (4 bit)

HRT : Hour tens in BCD code
bits : 20 - 21 (2 bit)

PM : AM/PM mark
bits : 22 - 22 (1 bit)


DTS

Date of time stamp register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DTS DTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAYU DAYT MONU MONT DOW

DAYU : Date units in BCD code
bits : 0 - 3 (4 bit)

DAYT : Date tens in BCD code
bits : 4 - 5 (2 bit)

MONU : Month units in BCD code
bits : 8 - 11 (4 bit)

MONT : Month tens in BCD code
bits : 12 - 12 (1 bit)

DOW : Week day units
bits : 13 - 15 (3 bit)


SSTS

Sub second of time stamp register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SSTS SSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSC

SSC : Sub second value
bits : 0 - 15 (16 bit)


HRFC

High resolution frequency compensation register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HRFC HRFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMSK CWND16 CWND8 FREQI

CMSK : Calibration mask number
bits : 0 - 8 (9 bit)

CWND16 : Frequency compensation window 16 second selected
bits : 13 - 13 (1 bit)

CWND8 : Frequency compensation window 8 second selected
bits : 14 - 14 (1 bit)

FREQI : Increase RTC frequency by 488.5ppm
bits : 15 - 15 (1 bit)


DATE

date register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATE DATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAYU DAYT MONU MONT DOW YRU YRT

DAYU : Date units in BCD format
bits : 0 - 3 (4 bit)

DAYT : Date tens in BCD format
bits : 4 - 5 (2 bit)

MONU : Month units in BCD format
bits : 8 - 11 (4 bit)

MONT : Month tens in BCD format
bits : 12 - 12 (1 bit)

DOW : Week day units
bits : 13 - 15 (3 bit)

YRU : Year units in BCD format
bits : 16 - 19 (4 bit)

YRT : Year tens in BCD format
bits : 20 - 23 (4 bit)


TAMP

Tamper register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAMP TAMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TP0EN TP0EG TPIE TP1EN TP1EG TPTS FREQ FLT PRCH DISPU PC13VAL PC13MDE PC14VAL PC14MDE PC15VAL PC15MDE

TP0EN : RTC_TAMP1 input detection enable
bits : 0 - 0 (1 bit)

TP0EG : Tamper 0 event trigger edge for RTC_TAMP0 input
bits : 1 - 1 (1 bit)

TPIE : Tamper detection interrupt enable
bits : 2 - 2 (1 bit)

TP1EN : Tamper 1 detection enable
bits : 3 - 3 (1 bit)

TP1EG : Tamper 1 event trigger edge for RTC_TAMP1 input
bits : 4 - 4 (1 bit)

TPTS : Make tamper function used for timestamp function
bits : 7 - 7 (1 bit)

FREQ : Sample frequency of tamper event detection
bits : 8 - 10 (3 bit)

FLT : RTC_TAMPx filter count setting
bits : 11 - 12 (2 bit)

PRCH : Precharge duration time of RTC_TAMPx
bits : 13 - 14 (2 bit)

DISPU : RTC_TAMPx pull up disable bit
bits : 15 - 15 (1 bit)

PC13VAL : Alarm output type control/PC13 output value
bits : 18 - 18 (1 bit)

PC13MDE : PC13 mode
bits : 19 - 19 (1 bit)

PC14VAL : PC14 value
bits : 20 - 20 (1 bit)

PC14MDE : PC14 mode
bits : 21 - 21 (1 bit)

PC15VAL : PC15 value
bits : 22 - 22 (1 bit)

PC15MDE : PC15 mode
bits : 23 - 23 (1 bit)


ALRM0SS

Alarm 0 sub second register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALRM0SS ALRM0SS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSC MSKSSC

SSC : Alarm sub second value
bits : 0 - 14 (15 bit)

MSKSSC : Mask control bit of SSC
bits : 24 - 27 (4 bit)


BKP0

backup register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BKP0 BKP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Backup domain registers
bits : 0 - 31 (32 bit)


BKP1

backup register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BKP1 BKP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Backup domain registers
bits : 0 - 31 (32 bit)


BKP2

backup register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BKP2 BKP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Backup domain registers
bits : 0 - 31 (32 bit)


BKP3

backup register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BKP3 BKP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Backup domain registers
bits : 0 - 31 (32 bit)


BKP4

backup register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BKP4 BKP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Backup domain registers
bits : 0 - 31 (32 bit)


CTL

control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSEG REFEN BPSHAD CS ALRM0EN TSEN ALRM0IE TSIE A1H S1H DSM COS OPOL OS COEN

TSEG : Valid event edge of time-stamp
bits : 3 - 3 (1 bit)
access : read-write

REFEN : Reference clock detection function enable
bits : 4 - 4 (1 bit)
access : read-write

BPSHAD : Shadow registers bypass control
bits : 5 - 5 (1 bit)
access : read-write

CS : Clock System
bits : 6 - 6 (1 bit)
access : read-write

ALRM0EN : Alarm-0 function enable
bits : 8 - 8 (1 bit)
access : read-write

TSEN : time-stamp function enable
bits : 11 - 11 (1 bit)
access : read-write

ALRM0IE : RTC alarm-0 interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

TSIE : Time-stamp interrupt enable
bits : 15 - 15 (1 bit)
access : read-write

A1H : Add 1 hour(summer time change
bits : 16 - 16 (1 bit)
access : write-only

S1H : Subtract 1 hour(winter time change)
bits : 17 - 17 (1 bit)
access : write-only

DSM : Daylight saving mark
bits : 18 - 18 (1 bit)
access : read-write

COS : Calibration output selection
bits : 19 - 19 (1 bit)
access : read-write

OPOL : Output polarity
bits : 20 - 20 (1 bit)
access : read-write

OS : Output selection
bits : 21 - 22 (2 bit)
access : read-write

COEN : Calibration output enable
bits : 23 - 23 (1 bit)
access : read-write


STAT

Status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALRM0WF SOPF YCM RSYNF INITF INITM ALRM0F TSF TSOVRF TP0F TP1F SCPF

ALRM0WF : Alarm 0 configuration can be write flag
bits : 0 - 0 (1 bit)
access : read-only

SOPF : Shift function operation pending flag
bits : 3 - 3 (1 bit)
access : read-only

YCM : Year configuration mark
bits : 4 - 4 (1 bit)
access : read-only

RSYNF : Register synchronization flag
bits : 5 - 5 (1 bit)
access : read-write

INITF : Initialization state flag
bits : 6 - 6 (1 bit)
access : read-only

INITM : enter initialization mode
bits : 7 - 7 (1 bit)
access : read-write

ALRM0F : Alarm-0 occurs flag
bits : 8 - 8 (1 bit)
access : read-write

TSF : Time-stamp flag
bits : 11 - 11 (1 bit)
access : read-write

TSOVRF : Time-stamp overflow flag
bits : 12 - 12 (1 bit)
access : read-write

TP0F : RTC_TAMP0 detected flag
bits : 13 - 13 (1 bit)
access : read-write

TP1F : RTC_TAMP1 detected flag
bits : 14 - 14 (1 bit)
access : read-write

SCPF : Smooth calibration pending flag
bits : 16 - 16 (1 bit)
access : read-only



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