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SLCD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTL

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

CFG

DATA6

DATA7

STAT

STATC


CTL

Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLCDON VSRC DUTY BIAS COMS

SLCDON : SLCD controller start
bits : 0 - 0 (1 bit)
access : read-write

VSRC : SLCD voltage source
bits : 1 - 1 (1 bit)
access : read-write

DUTY : Duty select
bits : 2 - 4 (3 bit)
access : read-write

BIAS : Bias select
bits : 5 - 6 (2 bit)
access : read-write

COMS : Common/segment padselect
bits : 7 - 7 (1 bit)
access : read-write


DATA0

SLCD display data register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA0 DATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG_DATA0

SEG_DATA0 : Each bit corresponds to one segment to display
bits : 0 - 31 (32 bit)
access : read-write


DATA1

SLCD display data register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA1 DATA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG_DATA1

SEG_DATA1 : Each bit corresponds to one segment to display
bits : 0 - 31 (32 bit)
access : read-write


DATA2

SLCD display data register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA2 DATA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG_DATA2

SEG_DATA2 : Each bit corresponds to one segment to display
bits : 0 - 31 (32 bit)
access : read-write


DATA3

SLCD display data register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA3 DATA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG_DATA3

SEG_DATA3 : Each bit corresponds to one segment to display
bits : 0 - 31 (32 bit)
access : read-write


DATA4

SLCD display data register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA4 DATA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG_DATA4

SEG_DATA4 : Each bit corresponds to one segment to display
bits : 0 - 31 (32 bit)
access : read-write


DATA5

SLCD display data register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA5 DATA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG_DATA5

SEG_DATA5 : Each bit corresponds to one segment to display
bits : 0 - 31 (32 bit)
access : read-write


CFG

SLCD configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HDEN SOFIE UPDIE PULSE DTD CONR BLKDIV BLKMOD DIV PSC

HDEN : High drive enable
bits : 0 - 0 (1 bit)
access : read-write

SOFIE : Start of frame interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

UPDIE : SLCD update done interrupt enable
bits : 3 - 3 (1 bit)
access : read-write

PULSE : Pulse on duration
bits : 4 - 6 (3 bit)
access : read-write

DTD : Dead time duration
bits : 7 - 9 (3 bit)
access : read-write

CONR : Contrast ratio
bits : 10 - 12 (3 bit)
access : read-write

BLKDIV : Blink frequency divider
bits : 13 - 15 (3 bit)
access : read-write

BLKMOD : Blink mode
bits : 16 - 17 (2 bit)
access : read-write

DIV : SLCD clock divider
bits : 18 - 21 (4 bit)
access : read-write

PSC : SLCD clock prescaler
bits : 22 - 25 (4 bit)
access : read-write


DATA6

SLCD display data register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA6 DATA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG_DATA6

SEG_DATA6 : Each bit corresponds to one segment to display
bits : 0 - 31 (32 bit)
access : read-write


DATA7

SLCD display data register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA7 DATA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG_DATA7

SEG_DATA7 : Each bit corresponds to one segment to display
bits : 0 - 31 (32 bit)
access : read-write


STAT

SLCD status flag register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ONF SOF UPRF UPDF VRDYF SYNF

ONF : SLCD controller on flag
bits : 0 - 0 (1 bit)
access : read-only

SOF : Start of frame flag
bits : 1 - 1 (1 bit)
access : read-only

UPRF : Update SLCD data request flag
bits : 2 - 2 (1 bit)
access : read-write

UPDF : Update SLCD data done flag
bits : 3 - 3 (1 bit)
access : read-only

VRDYF : SLCD voltage ready flag
bits : 4 - 4 (1 bit)
access : read-only

SYNF : SLCD_CFG register synchronization flag
bits : 5 - 5 (1 bit)
access : read-only


STATC

SLCD status flag clear register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATC STATC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOFC UPDC

SOFC : Start of frame flag clear
bits : 1 - 1 (1 bit)
access : read-write

UPDC : SLCD data update done clear bit
bits : 3 - 3 (1 bit)
access : read-write



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