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AFIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

EC

EXTISS2

EXTISS3

PCF1

PCF2

PCF0

PCF3

PCF4

PCF5

EXTISS0

EXTISS1


EC

Event control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EC EC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN PORT EOE

PIN : Event output pin selection
bits : 0 - 3 (4 bit)

PORT : Event output port selection
bits : 4 - 6 (3 bit)

EOE : Event output enable
bits : 7 - 7 (1 bit)


EXTISS2

EXTI sources selection register 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTISS2 EXTISS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI8_SS EXTI9_SS EXTI10_SS EXTI11_SS

EXTI8_SS : EXTI 8 sources selection
bits : 0 - 3 (4 bit)

EXTI9_SS : EXTI 9 sources selection
bits : 4 - 7 (4 bit)

EXTI10_SS : EXTI 10 sources selection
bits : 8 - 11 (4 bit)

EXTI11_SS : EXTI 11 sources selection
bits : 12 - 15 (4 bit)


EXTISS3

EXTI sources selection register 3
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTISS3 EXTISS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI12_SS EXTI13_SS EXTI14_SS EXTI15_SS

EXTI12_SS : EXTI 12 sources selection
bits : 0 - 3 (4 bit)

EXTI13_SS : EXTI 13 sources selection
bits : 4 - 7 (4 bit)

EXTI14_SS : EXTI 14 sources selection
bits : 8 - 11 (4 bit)

EXTI15_SS : EXTI 15 sources selection
bits : 12 - 15 (4 bit)


PCF1

AFIO port configuration register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCF1 PCF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER8_REMAP TIMER9_REMAP TIMER10_REMAP TIMER12_REMAP TIMER13_REMAP EXMC_NADV

TIMER8_REMAP : TIMER8 remapping
bits : 5 - 5 (1 bit)

TIMER9_REMAP : TIMER9 remapping
bits : 6 - 6 (1 bit)

TIMER10_REMAP : TIMER10 remapping
bits : 7 - 7 (1 bit)

TIMER12_REMAP : TIMER12 remapping
bits : 8 - 8 (1 bit)

TIMER13_REMAP : TIMER13 remapping
bits : 9 - 9 (1 bit)

EXMC_NADV : EXMC_NADV connect/disconnect
bits : 10 - 10 (1 bit)


PCF2

AFIO port configuration register 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCF2 PCF2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCI_VSYNC_REMAP DCI_D0_REMAP DCI_D1_REMAP DCI_D2_REMAP DCI_D3_REMAP DCI_D4_REMAP DCI_D5_REMAP DCI_D6_REMAP DCI_D7_REMAP DCI_D8_REMAP DCI_D9_REMAP DCI_D10_REMAP DCI_D11_REMAP DCI_D12_REMAP DCI_D13_REMAP DCI_HSYNC_REMAP PH01_REMAP

DCI_VSYNC_REMAP : DCI_VSYNC remapping
bits : 0 - 1 (2 bit)

DCI_D0_REMAP : DCI_D0 remapping
bits : 2 - 3 (2 bit)

DCI_D1_REMAP : DCI_D1 remapping
bits : 4 - 5 (2 bit)

DCI_D2_REMAP : DCI_D2 remapping
bits : 6 - 7 (2 bit)

DCI_D3_REMAP : DCI_D3 remapping
bits : 8 - 9 (2 bit)

DCI_D4_REMAP : DCI_D4 remapping
bits : 10 - 11 (2 bit)

DCI_D5_REMAP : DCI_D5 remapping
bits : 12 - 13 (2 bit)

DCI_D6_REMAP : DCI_D6 remapping
bits : 14 - 15 (2 bit)

DCI_D7_REMAP : DCI_D7 remapping
bits : 16 - 17 (2 bit)

DCI_D8_REMAP : DCI_D8 remapping
bits : 18 - 19 (2 bit)

DCI_D9_REMAP : DCI_D9 remapping
bits : 20 - 21 (2 bit)

DCI_D10_REMAP : DCI_D10 remapping
bits : 22 - 23 (2 bit)

DCI_D11_REMAP : DCI_D11 remapping
bits : 24 - 25 (2 bit)

DCI_D12_REMAP : DCI_D12 remapping
bits : 26 - 26 (1 bit)

DCI_D13_REMAP : DCI_D13 remapping
bits : 27 - 28 (2 bit)

DCI_HSYNC_REMAP : DCI_HSYNC remapping
bits : 29 - 29 (1 bit)

PH01_REMAP : PH0/PH1 remapping
bits : 31 - 31 (1 bit)


PCF0

AFIO port configuration register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCF0 PCF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI0_REMAP I2C0_REMAP USART0_REMAP USART1_REMAP USART2_REMAP TIMER0_REMAP TIMER1_REMAP TIMER2_REMAP TIMER3_REMAP CAN0_REMAP PD01_REMAP TIMER4CH3_IREMAP ADC0_ETRGINS_REMAP ADC0_ETRGREG_REMAP ADC1_ETRGINS_REMAP ADC1_ETRGREG_REMAP ENET_REMAP CAN1_REMAP ENET_PHY_SEL SWJ_CFG SPI2_REMAP TIMER1ITR0_REMAP PTP_PPS_REMAP

SPI0_REMAP : SPI0 remapping
bits : 0 - 0 (1 bit)

I2C0_REMAP : I2C0 remapping
bits : 1 - 1 (1 bit)

USART0_REMAP : USART0 remapping
bits : 2 - 2 (1 bit)

USART1_REMAP : USART1 remapping
bits : 3 - 3 (1 bit)

USART2_REMAP : USART2 remapping
bits : 4 - 5 (2 bit)

TIMER0_REMAP : TIMER0 remapping
bits : 6 - 7 (2 bit)

TIMER1_REMAP : TIMER1 remapping
bits : 8 - 9 (2 bit)

TIMER2_REMAP : TIMER2 remapping
bits : 10 - 11 (2 bit)

TIMER3_REMAP : TIMER3 remapping
bits : 12 - 12 (1 bit)

CAN0_REMAP : CAN0 alternate interface remapping
bits : 13 - 14 (2 bit)

PD01_REMAP : Port D0/Port D1 mapping on OSC_IN/OSC_OUT
bits : 15 - 15 (1 bit)

TIMER4CH3_IREMAP : TIMER4 channel3 internal remapping
bits : 16 - 16 (1 bit)

ADC0_ETRGINS_REMAP : ADC 0 external trigger inserted conversion remapping
bits : 17 - 17 (1 bit)

ADC0_ETRGREG_REMAP : ADC 0 external trigger regular conversion remapping
bits : 18 - 18 (1 bit)

ADC1_ETRGINS_REMAP : ADC 1 external trigger inserted conversion remapping
bits : 19 - 19 (1 bit)

ADC1_ETRGREG_REMAP : ADC 1 external trigger regular conversion remapping
bits : 20 - 20 (1 bit)

ENET_REMAP : Ethernet MAC I/O remapping
bits : 21 - 21 (1 bit)

CAN1_REMAP : CAN1 I/O remapping
bits : 22 - 22 (1 bit)

ENET_PHY_SEL : Ethernet MII or RMII PHY selection
bits : 23 - 23 (1 bit)

SWJ_CFG : Serial wire JTAG configuration
bits : 24 - 26 (3 bit)

SPI2_REMAP : SPI2/I2S2 remapping
bits : 28 - 28 (1 bit)

TIMER1ITR0_REMAP : TIMER1 internal trigger 0 remapping
bits : 29 - 29 (1 bit)

PTP_PPS_REMAP : Ethernet PTP PPS remapping
bits : 30 - 30 (1 bit)


PCF3

AFIO port configuration register 3
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCF3 PCF3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLI_B5_PA3_REMAP TLI_VSYNC_PA4_REMAP TLI_G2_PA6_REMAP TLI_R6_PA8_REMAP TLI_R4_PA11_REMAP TLI_R5_PA12_REMAP TLI_R3_PB0_REMAP TLI_R6_PB1_REMAP TLI_B6_PB8_REMAP TLI_B7_PB9_REMAP TLI_G4_PB10_REMAP TLI_G5_PB11_REMAP TLI_HSYNC_PC6_REMAP TLI_G6_PC7_REMAP TLI_R2_PC10_REMAP TLI_G7_PD3_REMAP TLI_B2_PD6_REMAP TLI_B3_PD10_REMAP TLI_B0_PE4_REMAP TLI_G0_PE5_REMAP TLI_G1_PE6_REMAP TLI_G3_PE11_REMAP TLI_B4_PE12_REMAP TLI_DE_PE13_REMAP TLI_CLK_PE14_REMAP TLI_R7_PE15_REMAP TLI_DE_PF10_REMAP TLI_R7_PG6_REMAP TLI_CLK_PG7_REMAP TLI_G3_PG10_REMAP TLI_B2_PG10_REMAP TLI_B3_PG11_REMAP

TLI_B5_PA3_REMAP : TLI_B5_PA3 remapping
bits : 0 - 0 (1 bit)

TLI_VSYNC_PA4_REMAP : TLI_VSYNC_PA4 remapping
bits : 1 - 1 (1 bit)

TLI_G2_PA6_REMAP : TLI_G2_PA6 remapping
bits : 2 - 2 (1 bit)

TLI_R6_PA8_REMAP : TLI_R6_PA8 remapping
bits : 3 - 3 (1 bit)

TLI_R4_PA11_REMAP : TLI_R4_PA11 remapping
bits : 4 - 4 (1 bit)

TLI_R5_PA12_REMAP : TLI_R5_PA12 remapping
bits : 5 - 5 (1 bit)

TLI_R3_PB0_REMAP : TLI_R3_PB0 remapping
bits : 6 - 6 (1 bit)

TLI_R6_PB1_REMAP : TLI_R6_PB1 remapping
bits : 7 - 7 (1 bit)

TLI_B6_PB8_REMAP : TLI_B6_PB8 remapping
bits : 8 - 8 (1 bit)

TLI_B7_PB9_REMAP : TLI_B7_PB9 remapping
bits : 9 - 9 (1 bit)

TLI_G4_PB10_REMAP : TLI_G4_PB10 remapping
bits : 10 - 10 (1 bit)

TLI_G5_PB11_REMAP : TLI_G5_PB11 remapping
bits : 11 - 11 (1 bit)

TLI_HSYNC_PC6_REMAP : TLI_HSYNC_PC6 remapping
bits : 12 - 12 (1 bit)

TLI_G6_PC7_REMAP : TLI_G6_PC7 remapping
bits : 13 - 13 (1 bit)

TLI_R2_PC10_REMAP : TLI_R2_PC10 remapping
bits : 14 - 14 (1 bit)

TLI_G7_PD3_REMAP : TLI_G7_PD3 remapping
bits : 15 - 15 (1 bit)

TLI_B2_PD6_REMAP : TLI_B2_PD6 remapping
bits : 16 - 16 (1 bit)

TLI_B3_PD10_REMAP : TLI_B3_PD10 remapping
bits : 17 - 17 (1 bit)

TLI_B0_PE4_REMAP : TLI_B0_PE4 remapping
bits : 18 - 18 (1 bit)

TLI_G0_PE5_REMAP : TLI_G0_PE5 remapping
bits : 19 - 19 (1 bit)

TLI_G1_PE6_REMAP : TLI_G1_PE6 remapping
bits : 20 - 20 (1 bit)

TLI_G3_PE11_REMAP : TLI_G3_PE11 remapping
bits : 21 - 21 (1 bit)

TLI_B4_PE12_REMAP : TLI_B4_PE12 remapping
bits : 22 - 22 (1 bit)

TLI_DE_PE13_REMAP : TLI_DE_PE13 remapping
bits : 23 - 23 (1 bit)

TLI_CLK_PE14_REMAP : TLI_CLK_PE14 remapping
bits : 24 - 24 (1 bit)

TLI_R7_PE15_REMAP : TLI_R7_PE15 remapping
bits : 25 - 25 (1 bit)

TLI_DE_PF10_REMAP : TLI_DE_PF10 remapping
bits : 26 - 26 (1 bit)

TLI_R7_PG6_REMAP : TLI_R7_PG6 remapping
bits : 27 - 27 (1 bit)

TLI_CLK_PG7_REMAP : TLI_CLK_PG7 remapping
bits : 28 - 28 (1 bit)

TLI_G3_PG10_REMAP : TLI_G3_PG10 remapping
bits : 29 - 29 (1 bit)

TLI_B2_PG10_REMAP : TLI_B2_PG10 remapping
bits : 30 - 30 (1 bit)

TLI_B3_PG11_REMAP : TLI_B3_PG11 remapping
bits : 31 - 31 (1 bit)


PCF4

AFIO port configuration register 4
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCF4 PCF4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLI_B4_PG12_REMAP TLI_B1_PG12_REMAP TLI_R0_PH2_REMAP TLI_R1_PH3_REMAP TLI_R2_PH8_REMAP TLI_R3_PH9_REMAP TLI_R4_PH10_REMAP TLI_R5_PH11_REMAP TLI_R6_PH12_REMAP TLI_G2_PH13_REMAP TLI_G3_PH14_REMAP TLI_G4_PH15_REMAP TLI_G5_PI0_REMAP TLI_G6_PI1_REMAP TLI_G7_PI2_REMAP TLI_B4_PI4_REMAP TLI_B5_PI5_REMAP TLI_B6_PI6_REMAP TLI_B7_PI7_REMAP TLI_VSYNC_PI9_REMAP TLI_HSYNC_PI10_REMAP TLI_R0_PH4_REMAP TLI_R1_PI3_REMAP SPI1_SCK_REMAP SPI2_MOSI_REMAP

TLI_B4_PG12_REMAP : TLI_B4_PG12 remapping
bits : 0 - 0 (1 bit)

TLI_B1_PG12_REMAP : TLI_B1_PG12 remapping
bits : 1 - 1 (1 bit)

TLI_R0_PH2_REMAP : TLI_R0_PH2 remapping
bits : 2 - 2 (1 bit)

TLI_R1_PH3_REMAP : TLI_R1_PH3 remapping
bits : 3 - 3 (1 bit)

TLI_R2_PH8_REMAP : TLI_R2_PH8 remapping
bits : 4 - 4 (1 bit)

TLI_R3_PH9_REMAP : TLI_R3_PH9 remapping
bits : 5 - 5 (1 bit)

TLI_R4_PH10_REMAP : TLI_R4_PH10 remapping
bits : 6 - 6 (1 bit)

TLI_R5_PH11_REMAP : TLI_R5_PH11 remapping
bits : 7 - 7 (1 bit)

TLI_R6_PH12_REMAP : TLI_R6_PH12 remapping
bits : 8 - 8 (1 bit)

TLI_G2_PH13_REMAP : TLI_G2_PH13 remapping
bits : 9 - 9 (1 bit)

TLI_G3_PH14_REMAP : TLI_G3_PH14 remapping
bits : 10 - 10 (1 bit)

TLI_G4_PH15_REMAP : TLI_G4_PH15 remapping
bits : 11 - 11 (1 bit)

TLI_G5_PI0_REMAP : TLI_G5_PI0 remapping
bits : 12 - 12 (1 bit)

TLI_G6_PI1_REMAP : TLI_G6_PI1 remapping
bits : 13 - 13 (1 bit)

TLI_G7_PI2_REMAP : TLI_G7_PI2 remapping
bits : 14 - 14 (1 bit)

TLI_B4_PI4_REMAP : TLI_B4_PI4 remapping
bits : 15 - 15 (1 bit)

TLI_B5_PI5_REMAP : TLI_B5_PI5 remapping
bits : 16 - 16 (1 bit)

TLI_B6_PI6_REMAP : TLI_B6_PI6 remapping
bits : 17 - 17 (1 bit)

TLI_B7_PI7_REMAP : TLI_B7_PI7 remapping
bits : 18 - 18 (1 bit)

TLI_VSYNC_PI9_REMAP : TLI_VSYNC_PI9 remapping
bits : 19 - 19 (1 bit)

TLI_HSYNC_PI10_REMAP : TLI_HSYNC_PI10 remapping
bits : 20 - 20 (1 bit)

TLI_R0_PH4_REMAP : TLI_R0_PH4 remapping
bits : 21 - 21 (1 bit)

TLI_R1_PI3_REMAP : TLI_R1_PI3 remapping
bits : 22 - 22 (1 bit)

SPI1_SCK_REMAP : SPI1_SCK remapping
bits : 23 - 23 (1 bit)

SPI2_MOSI_REMAP : SPI2_MOSI remapping
bits : 24 - 24 (1 bit)


PCF5

AFIO port configuration register 5
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCF5 PCF5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C2_REMAP0 I2C2_REMAP1 TIMER1_CH0_REMAP TIMER4_REMAP TIMER7_CHON_REMAP TIMER7_CH_REMAP I2C1_REMAP SPI1_NSCK_REMAP SPI1_IO_REMAP UART3_REMAP TIMER11_REMAP CAN0_ADD_REMAP ENET_TXD3_REMAP PPS_HI_REMAP ENET_TXD01_REMAP ENET_CRSCOL_REMAP ENET_RX_HI_REMAP UART6_REMAP USART5_CK_REMAP USART5_RTS_REMAP USART5_CTS_REMAP USART5_TX_REMAP USART5_RX_REMAP EXMC_SDNWE_REMAP EXMC_SDCKE0_REMAP EXMC_SDCKE1_REMAP EXMC_SDNE0_REMAP EXMC_SDNE1_REMAP

I2C2_REMAP0 : I2C2 remapping 0
bits : 0 - 0 (1 bit)

I2C2_REMAP1 : I2C2 remapping 1
bits : 1 - 1 (1 bit)

TIMER1_CH0_REMAP : TIMER1_CH0 remapping
bits : 2 - 2 (1 bit)

TIMER4_REMAP : TIMER4 remapping
bits : 3 - 3 (1 bit)

TIMER7_CHON_REMAP : TIMER7_CHON remapping
bits : 4 - 5 (2 bit)

TIMER7_CH_REMAP : TIMER7_CH remapping
bits : 6 - 6 (1 bit)

I2C1_REMAP : I2C1 remapping
bits : 7 - 8 (2 bit)

SPI1_NSCK_REMAP : SPI1_NSCK remapping
bits : 9 - 10 (2 bit)

SPI1_IO_REMAP : SPI1_IO remapping
bits : 11 - 12 (2 bit)

UART3_REMAP : UART3 remapping
bits : 13 - 13 (1 bit)

TIMER11_REMAP : TIMER11 remapping
bits : 14 - 14 (1 bit)

CAN0_ADD_REMAP : CAN0_ADD remapping
bits : 15 - 15 (1 bit)

ENET_TXD3_REMAP : ENET _TXD3 remapping
bits : 16 - 16 (1 bit)

PPS_HI_REMAP : PPS_HI remapping
bits : 17 - 17 (1 bit)

ENET_TXD01_REMAP : ENET_TXD01 remapping
bits : 18 - 18 (1 bit)

ENET_CRSCOL_REMAP : ENET_CRSCOL remapping
bits : 19 - 19 (1 bit)

ENET_RX_HI_REMAP : ENET _RX_HI remapping
bits : 20 - 20 (1 bit)

UART6_REMAP : UART6 remapping
bits : 21 - 21 (1 bit)

USART5_CK_REMAP : USART5_CK remapping
bits : 22 - 22 (1 bit)

USART5_RTS_REMAP : USART5_RTS remapping
bits : 23 - 23 (1 bit)

USART5_CTS_REMAP : USART5_CTS remapping
bits : 24 - 24 (1 bit)

USART5_TX_REMAP : USART5_TX remapping
bits : 25 - 25 (1 bit)

USART5_RX_REMAP : USART5_RX remapping
bits : 26 - 26 (1 bit)

EXMC_SDNWE_REMAP : EXMC_SDNWE remapping
bits : 27 - 27 (1 bit)

EXMC_SDCKE0_REMAP : EXMC_SDCKE0 remapping
bits : 28 - 28 (1 bit)

EXMC_SDCKE1_REMAP : EXMC_SDCKE1 remapping
bits : 29 - 29 (1 bit)

EXMC_SDNE0_REMAP : EXMC_SDNE0 remapping
bits : 30 - 30 (1 bit)

EXMC_SDNE1_REMAP : EXMC_SDNE1 remapping
bits : 31 - 31 (1 bit)


EXTISS0

EXTI sources selection register 0
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTISS0 EXTISS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0_SS EXTI1_SS EXTI2_SS EXTI3_SS

EXTI0_SS : EXTI 0 sources selection
bits : 0 - 3 (4 bit)

EXTI1_SS : EXTI 1 sources selection
bits : 4 - 7 (4 bit)

EXTI2_SS : EXTI 2 sources selection
bits : 8 - 11 (4 bit)

EXTI3_SS : EXTI 3 sources selection
bits : 12 - 15 (4 bit)


EXTISS1

EXTI sources selection register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTISS1 EXTISS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI4_SS EXTI5_SS EXTI6_SS EXTI7_SS

EXTI4_SS : EXTI 4 sources selection
bits : 0 - 3 (4 bit)

EXTI5_SS : EXTI 5 sources selection
bits : 4 - 7 (4 bit)

EXTI6_SS : EXTI 6 sources selection
bits : 8 - 11 (4 bit)

EXTI7_SS : EXTI 7 sources selection
bits : 12 - 15 (4 bit)



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