\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
CAU control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAUDIR : CAU direction
bits : 2 - 2 (1 bit)
access : read-write
ALGM : Encryption/decryption algorithm mode
bits : 3 - 5 (3 bit)
access : read-write
DATAM : Data swapping type mode configuration
bits : 6 - 7 (2 bit)
access : read-write
KEYM : AES key size mode configuration
bits : 8 - 9 (2 bit)
access : read-write
FFLUSH : FIFO flush
bits : 14 - 14 (1 bit)
access : write-only
CAUEN : Cryptographic module enable
bits : 15 - 15 (1 bit)
access : read-write
CAU DMA enable register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAIEN : In FIFO DMA enable
bits : 0 - 0 (1 bit)
DMAOEN : Out FIFO DMA enable
bits : 1 - 1 (1 bit)
CAU interrupt enable register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IINTEN : In FIFO interrupt enable
bits : 0 - 0 (1 bit)
OINTEN : Out FIFO interrupt enable
bits : 1 - 1 (1 bit)
CAU interrupt status flag register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ISTA : In FIFO interrupt flag
bits : 0 - 0 (1 bit)
OSTA : Out FIFO interrupt flag
bits : 1 - 1 (1 bit)
CAU enable interrupt status flag register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IINTF : In FIFO enabled interrupt flag
bits : 0 - 0 (1 bit)
OINTF : Out FIFO enabled interrupt flag
bits : 1 - 1 (1 bit)
CAU key register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY0H : Key for DES,TDES,AES
bits : 0 - 31 (32 bit)
CAU key register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY0L : Key for DES,TDES,AES
bits : 0 - 31 (32 bit)
CAU key register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY1H : Key for DES,TDES,AES
bits : 0 - 31 (32 bit)
CAU key register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY1L : Key for DES,TDES,AES
bits : 0 - 31 (32 bit)
CAU key register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY2H : Key for DES,TDES,AES
bits : 0 - 31 (32 bit)
CAU key register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY2L : Key for DES,TDES,AES
bits : 0 - 31 (32 bit)
CAU key register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY3H : Key for DES,TDES,AES
bits : 0 - 31 (32 bit)
CAU key register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY3L : Key for DES,TDES,AES
bits : 0 - 31 (32 bit)
CAU status register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IEM : IN FIFO empty flag
bits : 0 - 0 (1 bit)
INF : IN FIFO not full flag
bits : 1 - 1 (1 bit)
ONE : OUT FIFO not empty flag
bits : 2 - 2 (1 bit)
OFU : OUT FIFO full flag
bits : 3 - 3 (1 bit)
BUSY : BUSY flag
bits : 4 - 4 (1 bit)
CAU initialization register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IV0H : The initialization vector for DES,TDES,AES
bits : 0 - 31 (32 bit)
CAU initialization register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IV0L : The initialization vector for DES,TDES,AES
bits : 0 - 31 (32 bit)
CAU initialization register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IV1H : The initialization vector for DES,TDES,AES
bits : 0 - 31 (32 bit)
CAU initialization register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IV1L : The initialization vector for DES,TDES,AES
bits : 0 - 31 (32 bit)
CAU data input register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DI : Data input
bits : 0 - 31 (32 bit)
CAU data output register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DO : Data output
bits : 0 - 31 (32 bit)
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