RCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

add a new register to this peripheral

CTL

APB1RST

AHB1EN

APB2EN

APB1EN

BDCTL

RSTSCK

AHB1RST

CFG1

DSV

CFG0

AHB2EN

ADDAPB2EN

ADDAPB1EN

AHB2RST

ADDAPB2RST

ADDAPB1RST

INT

CFG2

PLLTCTL

PLLTINT

PLLTCFG

APB2RST


CTL

Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRC8MEN IRC8MSTB IRC8MADJ IRC8MCALIB HXTALEN HXTALSTB HXTALBPS CKMEN PLLEN PLLSTB PLL1EN PLL1STB PLL2EN PLL2STB

IRC8MEN : Internal 8MHz RC oscillator Enable
bits : 0 - 0 (1 bit)
access : read-write

IRC8MSTB : IRC8M Internal 8MHz RC Oscillator stabilization Flag
bits : 1 - 1 (1 bit)
access : read-only

IRC8MADJ : Internal 8MHz RC Oscillator clock trim adjust value
bits : 3 - 7 (5 bit)
access : read-write

IRC8MCALIB : Internal 8MHz RC Oscillator calibration value register
bits : 8 - 15 (8 bit)
access : read-only

HXTALEN : External High Speed oscillator Enable
bits : 16 - 16 (1 bit)
access : read-write

HXTALSTB : External crystal oscillator (HXTAL) clock stabilization flag
bits : 17 - 17 (1 bit)
access : read-only

HXTALBPS : External crystal oscillator (HXTAL) clock bypass mode enable
bits : 18 - 18 (1 bit)
access : read-write

CKMEN : HXTAL Clock Monitor Enable
bits : 19 - 19 (1 bit)
access : read-write

PLLEN : PLL enable
bits : 24 - 24 (1 bit)
access : read-write

PLLSTB : PLL Clock Stabilization Flag
bits : 25 - 25 (1 bit)
access : read-only

PLL1EN : PLL1 enable
bits : 26 - 26 (1 bit)
access : read-write

PLL1STB : PLL1 Clock Stabilization Flag
bits : 27 - 27 (1 bit)
access : read-only

PLL2EN : PLL2 enable
bits : 28 - 28 (1 bit)
access : read-write

PLL2STB : PLL2 Clock Stabilization Flag
bits : 29 - 29 (1 bit)
access : read-only


APB1RST

APB1 reset register (RCU_APB1RST)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1RST APB1RST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER1RST TIMER2RST TIMER3RST TIMER4RST TIMER5RST TIMER6RST TIMER11RST TIMER12RST TIMER13RST WWDGTRST SPI1RST SPI2RST USART1RST USART2RST UART3RST UART4RST I2C0RST I2C1RST CAN0RST CAN1RST BKPIRST PMURST DACRST

TIMER1RST : TIMER1 timer reset
bits : 0 - 0 (1 bit)

TIMER2RST : TIMER2 timer reset
bits : 1 - 1 (1 bit)

TIMER3RST : TIMER3 timer reset
bits : 2 - 2 (1 bit)

TIMER4RST : TIMER4 timer reset
bits : 3 - 3 (1 bit)

TIMER5RST : TIMER5 timer reset
bits : 4 - 4 (1 bit)

TIMER6RST : TIMER6 timer reset
bits : 5 - 5 (1 bit)

TIMER11RST : TIMER11 timer reset
bits : 6 - 6 (1 bit)

TIMER12RST : TIMER12 timer reset
bits : 7 - 7 (1 bit)

TIMER13RST : TIMER13 timer reset
bits : 8 - 8 (1 bit)

WWDGTRST : Window watchdog timer reset
bits : 11 - 11 (1 bit)

SPI1RST : SPI1 reset
bits : 14 - 14 (1 bit)

SPI2RST : SPI2 reset
bits : 15 - 15 (1 bit)

USART1RST : USART1 reset
bits : 17 - 17 (1 bit)

USART2RST : USART2 reset
bits : 18 - 18 (1 bit)

UART3RST : UART3 reset
bits : 19 - 19 (1 bit)

UART4RST : UART4 reset
bits : 20 - 20 (1 bit)

I2C0RST : I2C0 reset
bits : 21 - 21 (1 bit)

I2C1RST : I2C1 reset
bits : 22 - 22 (1 bit)

CAN0RST : CAN0 reset
bits : 25 - 25 (1 bit)

CAN1RST : CAN1 reset
bits : 26 - 26 (1 bit)

BKPIRST : Backup interface reset
bits : 27 - 27 (1 bit)

PMURST : Power control reset
bits : 28 - 28 (1 bit)

DACRST : DAC reset
bits : 29 - 29 (1 bit)


AHB1EN

AHB1 enable register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB1EN AHB1EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA0EN DMA1EN SRAMSPEN FMCSPEN CRCEN EXMCEN SDIOEN USBFSEN ENETEN ENETTXEN ENETRXEN

DMA0EN : DMA0 clock enable
bits : 0 - 0 (1 bit)

DMA1EN : DMA1 clock enable
bits : 1 - 1 (1 bit)

SRAMSPEN : SRAM interface clock enable when sleep mode
bits : 2 - 2 (1 bit)

FMCSPEN : FMC clock enable when sleep mode
bits : 4 - 4 (1 bit)

CRCEN : CRC clock enable
bits : 6 - 6 (1 bit)

EXMCEN : EXMC clock enable
bits : 8 - 8 (1 bit)

SDIOEN : SDIO clock enable
bits : 10 - 10 (1 bit)

USBFSEN : USBFS clock enable
bits : 12 - 12 (1 bit)

ENETEN : Ethernet clock enable
bits : 14 - 14 (1 bit)

ENETTXEN : Ethernet TX clock enable
bits : 15 - 15 (1 bit)

ENETRXEN : Ethernet RX clock enable
bits : 16 - 16 (1 bit)


APB2EN

APB2 clock enable register (RCU_APB2EN)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2EN APB2EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFEN PAEN PBEN PCEN PDEN PEEN PFEN PGEN ADC0EN ADC1EN TIMER0EN SPI0EN TIMER7EN USART0EN ADC2EN TIMER8EN TIMER9EN TIMER10EN

AFEN : Alternate function IO clock enable
bits : 0 - 0 (1 bit)

PAEN : GPIO port A clock enable
bits : 2 - 2 (1 bit)

PBEN : GPIO port B clock enable
bits : 3 - 3 (1 bit)

PCEN : GPIO port C clock enable
bits : 4 - 4 (1 bit)

PDEN : GPIO port D clock enable
bits : 5 - 5 (1 bit)

PEEN : GPIO port E clock enable
bits : 6 - 6 (1 bit)

PFEN : GPIO port F clock enable
bits : 7 - 7 (1 bit)

PGEN : GPIO port G clock enable
bits : 8 - 8 (1 bit)

ADC0EN : ADC0 clock enable
bits : 9 - 9 (1 bit)

ADC1EN : ADC1 clock enable
bits : 10 - 10 (1 bit)

TIMER0EN : TIMER0 clock enable
bits : 11 - 11 (1 bit)

SPI0EN : SPI0 clock enable
bits : 12 - 12 (1 bit)

TIMER7EN : TIMER7 clock enable
bits : 13 - 13 (1 bit)

USART0EN : USART0 clock enable
bits : 14 - 14 (1 bit)

ADC2EN : ADC2 clock enable
bits : 15 - 15 (1 bit)

TIMER8EN : TIMER8 clock enable
bits : 19 - 19 (1 bit)

TIMER9EN : TIMER9 clock enable
bits : 20 - 20 (1 bit)

TIMER10EN : TIMER10 clock enable
bits : 21 - 21 (1 bit)


APB1EN

APB1 clock enable register (RCU_APB1EN)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1EN APB1EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER1EN TIMER2EN TIMER3EN TIMER4EN TIMER5EN TIMER6EN TIMER11EN TIMER12EN TIMER13EN WWDGTEN SPI1EN SPI2EN USART1EN USART2EN UART3EN UART4EN I2C0EN I2C1EN CAN0EN CAN1EN BKPIEN PMUEN DACEN

TIMER1EN : TIMER1 timer clock enable
bits : 0 - 0 (1 bit)

TIMER2EN : TIMER2 timer clock enable
bits : 1 - 1 (1 bit)

TIMER3EN : TIMER3 timer clock enable
bits : 2 - 2 (1 bit)

TIMER4EN : TIMER4 timer clock enable
bits : 3 - 3 (1 bit)

TIMER5EN : TIMER5 timer clock enable
bits : 4 - 4 (1 bit)

TIMER6EN : TIMER6 timer clock enable
bits : 5 - 5 (1 bit)

TIMER11EN : TIMER11 timer clock enable
bits : 6 - 6 (1 bit)

TIMER12EN : TIMER12 timer clock enable
bits : 7 - 7 (1 bit)

TIMER13EN : TIMER13 timer clock enable
bits : 8 - 8 (1 bit)

WWDGTEN : Window watchdog timer clock enable
bits : 11 - 11 (1 bit)

SPI1EN : SPI1 clock enable
bits : 14 - 14 (1 bit)

SPI2EN : SPI2 clock enable
bits : 15 - 15 (1 bit)

USART1EN : USART1 clock enable
bits : 17 - 17 (1 bit)

USART2EN : USART2 clock enable
bits : 18 - 18 (1 bit)

UART3EN : UART3 clock enable
bits : 19 - 19 (1 bit)

UART4EN : UART4 clock enable
bits : 20 - 20 (1 bit)

I2C0EN : I2C0 clock enable
bits : 21 - 21 (1 bit)

I2C1EN : I2C1 clock enable
bits : 22 - 22 (1 bit)

CAN0EN : CAN0 clock enable
bits : 25 - 25 (1 bit)

CAN1EN : CAN1 clock enable
bits : 26 - 26 (1 bit)

BKPIEN : Backup interface clock enable
bits : 27 - 27 (1 bit)

PMUEN : Power control clock enable
bits : 28 - 28 (1 bit)

DACEN : DAC clock enable
bits : 29 - 29 (1 bit)


BDCTL

Backup domain control register (RCU_BDCTL)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDCTL BDCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LXTALEN LXTALSTB LXTALBPS LXTALDRI RTCSRC RTCEN BKPRST

LXTALEN : LXTAL enable
bits : 0 - 0 (1 bit)
access : read-write

LXTALSTB : External low-speed oscillator stabilization
bits : 1 - 1 (1 bit)
access : read-only

LXTALBPS : LXTAL bypass mode enable
bits : 2 - 2 (1 bit)
access : read-write

LXTALDRI : LXTAL drive capability
bits : 3 - 4 (2 bit)
access : read-write

RTCSRC : RTC clock entry selection
bits : 8 - 9 (2 bit)
access : read-write

RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)
access : read-write

BKPRST : Backup domain reset
bits : 16 - 16 (1 bit)
access : read-write


RSTSCK

Reset source /clock register (RCU_RSTSCK)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTSCK RSTSCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRC40KEN IRC40KSTB RSTFC EPRSTF PORRSTF SWRSTF FWDGTRSTF WWDGTRSTF LPRSTF

IRC40KEN : IRC40K enable
bits : 0 - 0 (1 bit)
access : read-write

IRC40KSTB : IRC40K stabilization
bits : 1 - 1 (1 bit)
access : read-only

RSTFC : Reset flag clear
bits : 24 - 24 (1 bit)
access : read-write

EPRSTF : External PIN reset flag
bits : 26 - 26 (1 bit)
access : read-only

PORRSTF : Power reset flag
bits : 27 - 27 (1 bit)
access : read-only

SWRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-only

FWDGTRSTF : Free Watchdog timer reset flag
bits : 29 - 29 (1 bit)
access : read-only

WWDGTRSTF : Window watchdog timer reset flag
bits : 30 - 30 (1 bit)
access : read-only

LPRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
access : read-only


AHB1RST

AHB1 reset register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB1RST AHB1RST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBFSRST ENETRST

USBFSRST : USBFS reset
bits : 12 - 12 (1 bit)

ENETRST : ENET reset
bits : 14 - 14 (1 bit)


CFG1

Clock Configuration register 1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG1 CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREDV0 PREDV1 PLL1MF PLL2MF PREDV0SEL I2S1SEL I2S2SEL

PREDV0 : PREDV0 division factor
bits : 0 - 3 (4 bit)

PREDV1 : PREDV1 division factor
bits : 4 - 7 (4 bit)

PLL1MF : The PLL1 clock multiplication factor
bits : 8 - 11 (4 bit)

PLL2MF : The PLL2 clock multiplication factor
bits : 12 - 15 (4 bit)

PREDV0SEL : PREDV0 input Clock Source Selection
bits : 16 - 16 (1 bit)

I2S1SEL : I2S1 Clock Source Selection
bits : 17 - 17 (1 bit)

I2S2SEL : I2S2 Clock Source Selection
bits : 18 - 18 (1 bit)


DSV

Deep sleep mode Voltage register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSV DSV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSLPVS

DSLPVS : Deep-sleep mode voltage select
bits : 0 - 2 (3 bit)
access : read-write


CFG0

Clock configuration register 0 (RCU_CFG0)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG0 CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCS SCSS AHBPSC APB1PSC APB2PSC ADCPSC_1_0 PLLSEL PREDV0_LSB PLLMF_3_0 USBFSPSC CKOUT0SEL ADCPSC_2 PLLMF_4

SCS : System clock switch
bits : 0 - 1 (2 bit)
access : read-write

SCSS : System clock switch status
bits : 2 - 3 (2 bit)
access : read-only

AHBPSC : AHB prescaler selection
bits : 4 - 7 (4 bit)
access : read-write

APB1PSC : APB1 prescaler selection
bits : 8 - 10 (3 bit)
access : read-write

APB2PSC : APB2 prescaler selection
bits : 11 - 13 (3 bit)
access : read-write

ADCPSC_1_0 : ADC clock prescaler selection
bits : 14 - 15 (2 bit)
access : read-write

PLLSEL : PLL Clock Source Selection
bits : 16 - 16 (1 bit)
access : read-write

PREDV0_LSB : The LSB of PREDV0 division factor
bits : 17 - 17 (1 bit)
access : read-write

PLLMF_3_0 : The PLL clock multiplication factor
bits : 18 - 21 (4 bit)
access : read-write

USBFSPSC : USBFS clock prescaler selection
bits : 22 - 23 (2 bit)
access : read-write

CKOUT0SEL : CKOUT0 Clock Source Selection
bits : 24 - 27 (4 bit)
access : read-write

ADCPSC_2 : Bit 2 of ADCPSC
bits : 28 - 28 (1 bit)
access : read-write

PLLMF_4 : Bit 4 of PLLMF
bits : 29 - 29 (1 bit)
access : read-write


AHB2EN

AHB2 enable register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB2EN AHB2EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCIEN CAUEN HAUEN TRNGEN

DCIEN : DCI clock enable
bits : 0 - 0 (1 bit)

CAUEN : CAU clock enable
bits : 4 - 4 (1 bit)

HAUEN : HAU clock enable
bits : 5 - 5 (1 bit)

TRNGEN : TRNG clock enable
bits : 6 - 6 (1 bit)


ADDAPB2EN

APB2 additional enable register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDAPB2EN ADDAPB2EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART5EN TLIEN PHEN PIEN

USART5EN : USART5 clock enable
bits : 24 - 24 (1 bit)

TLIEN : TLI clock enable
bits : 26 - 26 (1 bit)

PHEN : GPIO port H clock enable
bits : 30 - 30 (1 bit)

PIEN : GPIO port I clock enable
bits : 31 - 31 (1 bit)


ADDAPB1EN

APB1 additional enable register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDAPB1EN ADDAPB1EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C2EN UART6EN UART7EN

I2C2EN : I2C2 clock enable
bits : 23 - 23 (1 bit)

UART6EN : UART6 clock enable
bits : 30 - 30 (1 bit)

UART7EN : UART7 clock enable
bits : 31 - 31 (1 bit)


AHB2RST

AHB2 reset register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB2RST AHB2RST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCIRST CAURST HAURST TRNGRST

DCIRST : DCI reset
bits : 0 - 0 (1 bit)

CAURST : CAU reset
bits : 4 - 4 (1 bit)

HAURST : HAU reset
bits : 5 - 5 (1 bit)

TRNGRST : TRNG reset
bits : 6 - 6 (1 bit)


ADDAPB2RST

APB2 additional enable register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDAPB2RST ADDAPB2RST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART5RST TLIRST PHRST PIRST

USART5RST : USART5 reset
bits : 24 - 24 (1 bit)

TLIRST : TLI reset
bits : 26 - 26 (1 bit)

PHRST : GPIO port H reset
bits : 30 - 30 (1 bit)

PIRST : GPIO port I reset
bits : 31 - 31 (1 bit)


ADDAPB1RST

APB1 additional enable register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDAPB1RST ADDAPB1RST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C2RST UART6RST UART7RST

I2C2RST : I2C2 reset
bits : 23 - 23 (1 bit)

UART6RST : UART6 reset
bits : 30 - 30 (1 bit)

UART7RST : UART7 reset
bits : 31 - 31 (1 bit)


INT

Clock interrupt register (RCU_INT)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRC40KSTBIF LXTALSTBIF IRC8MSTBIF HXTALSTBIF PLLSTBIF PLL1STBIF PLL2STBIF CKMIF IRC40KSTBIE LXTALSTBIE IRC8MSTBIE HXTALSTBIE PLLSTBIE PLL1STBIE PLL2STBIE IRC40KSTBIC LXTALSTBIC IRC8MSTBIC HXTALSTBIC PLLSTBIC PLL1STBIC PLL2STBIC CKMIC

IRC40KSTBIF : IRC40K stabilization interrupt flag
bits : 0 - 0 (1 bit)
access : read-only

LXTALSTBIF : LXTAL stabilization interrupt flag
bits : 1 - 1 (1 bit)
access : read-only

IRC8MSTBIF : IRC8M stabilization interrupt flag
bits : 2 - 2 (1 bit)
access : read-only

HXTALSTBIF : HXTAL stabilization interrupt flag
bits : 3 - 3 (1 bit)
access : read-only

PLLSTBIF : PLL stabilization interrupt flag
bits : 4 - 4 (1 bit)
access : read-only

PLL1STBIF : PLL1 stabilization interrupt flag
bits : 5 - 5 (1 bit)
access : read-only

PLL2STBIF : PLL2 stabilization interrupt flag
bits : 6 - 6 (1 bit)
access : read-only

CKMIF : HXTAL Clock Stuck Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-only

IRC40KSTBIE : IRC40K Stabilization interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

LXTALSTBIE : LXTAL Stabilization Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

IRC8MSTBIE : IRC8M Stabilization Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

HXTALSTBIE : HXTAL Stabilization Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

PLLSTBIE : PLL Stabilization Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write

PLL1STBIE : PLL1 Stabilization Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write

PLL2STBIE : PLL2 Stabilization Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write

IRC40KSTBIC : IRC40K Stabilization Interrupt Clear
bits : 16 - 16 (1 bit)
access : write-only

LXTALSTBIC : LXTAL Stabilization Interrupt Clear
bits : 17 - 17 (1 bit)
access : write-only

IRC8MSTBIC : IRC8M Stabilization Interrupt Clear
bits : 18 - 18 (1 bit)
access : write-only

HXTALSTBIC : HXTAL Stabilization Interrupt Clear
bits : 19 - 19 (1 bit)
access : write-only

PLLSTBIC : PLL stabilization Interrupt Clear
bits : 20 - 20 (1 bit)
access : write-only

PLL1STBIC : PLL1 stabilization Interrupt Clear
bits : 21 - 21 (1 bit)
access : write-only

PLL2STBIC : PLL2 stabilization Interrupt Clear
bits : 22 - 22 (1 bit)
access : write-only

CKMIC : HXTAL Clock Stuck Interrupt Clear
bits : 23 - 23 (1 bit)
access : write-only


CFG2

configuration register 2
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG2 CFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKOUT0DIV CKOUT1DIV CKOUT1SEL

CKOUT0DIV : the CK_OUT0 divider
bits : 0 - 5 (6 bit)
access : read-write

CKOUT1DIV : the CK_OUT1 divider
bits : 8 - 13 (6 bit)
access : read-write

CKOUT1SEL : CK_OUT1 clock source selection
bits : 16 - 19 (4 bit)
access : read-write


PLLTCTL

PLLT control register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLTCTL PLLTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLTEN PLLTSTB

PLLTEN : PLLT enable
bits : 28 - 28 (1 bit)
access : read-write

PLLTSTB : PLLTclock stabilization flag
bits : 29 - 29 (1 bit)
access : read-only


PLLTINT

PLLT interrupt register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLTINT PLLTINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLTSTBIF PLLTSTBIE PLLTSTBIC

PLLTSTBIF : PLLT stabilization interrupt flag
bits : 6 - 6 (1 bit)
access : read-only

PLLTSTBIE : PLLT stabilization Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write

PLLTSTBIC : PLLT stabilization Interrupt clear
bits : 22 - 22 (1 bit)
access : read-write


PLLTCFG

PLLT configuration register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLTCFG PLLTCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLTPSC PLLTMF TLIPSC PLLTRPSC PLLTSEL

PLLTPSC : PLLT prescaler selection
bits : 0 - 5 (6 bit)
access : read-write

PLLTMF : PLLT multiply factor for VCO
bits : 6 - 14 (9 bit)
access : read-write

TLIPSC : TLI prescaler selection
bits : 16 - 17 (2 bit)
access : read-write

PLLTRPSC : PLLTR prescaler selection
bits : 28 - 30 (3 bit)
access : read-write

PLLTSEL : PLLT clock source select
bits : 31 - 31 (1 bit)
access : read-write


APB2RST

APB2 reset register (RCU_APB2RST)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2RST APB2RST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFRST PARST PBRST PCRST PDRST PERST PFRST PGRST ADC0RST ADC1RST TIMER0RST SPI0RST TIMER7RST USART0RST ADC2RST TIMER8RST TIMER9RST TIMER10RST

AFRST : Alternate function I/O reset
bits : 0 - 0 (1 bit)

PARST : GPIO port A reset
bits : 2 - 2 (1 bit)

PBRST : GPIO port B reset
bits : 3 - 3 (1 bit)

PCRST : GPIO port C reset
bits : 4 - 4 (1 bit)

PDRST : GPIO port D reset
bits : 5 - 5 (1 bit)

PERST : GPIO port E reset
bits : 6 - 6 (1 bit)

PFRST : GPIO portF reset
bits : 7 - 7 (1 bit)

PGRST : GPIO port G reset
bits : 8 - 8 (1 bit)

ADC0RST : ADC0 reset
bits : 9 - 9 (1 bit)

ADC1RST : ADC1 reset
bits : 10 - 10 (1 bit)

TIMER0RST : Timer 0 reset
bits : 11 - 11 (1 bit)

SPI0RST : SPI0 reset
bits : 12 - 12 (1 bit)

TIMER7RST : Timer 7 reset
bits : 13 - 13 (1 bit)

USART0RST : USART0 Reset
bits : 14 - 14 (1 bit)

ADC2RST : ADC2 reset
bits : 15 - 15 (1 bit)

TIMER8RST : Timer 8 reset
bits : 19 - 19 (1 bit)

TIMER9RST : Timer 9 reset
bits : 20 - 20 (1 bit)

TIMER10RST : Timer 10 reset
bits : 21 - 21 (1 bit)



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