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FMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

WS

CTL0

PID

ADDR0

OBCTL

WPR

KEY

KEY1

STAT1

CTL1

ADDR1

OBKEY

STAT0

WSEN


WS

wait state counter register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WS WS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WSCNT

WSCNT : wait state counter register
bits : 0 - 2 (3 bit)


CTL0

Control register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL0 CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PG PER MER OBPG OBER START LK OBWPE ERIE ENDIE

PG : Main flash program for bank0 command bit
bits : 0 - 0 (1 bit)

PER : Main flash page erase for bank0 command bit
bits : 1 - 1 (1 bit)

MER : Main flash mass erase for bank0 command bit
bits : 2 - 2 (1 bit)

OBPG : Option bytes program command bit
bits : 4 - 4 (1 bit)

OBER : Option bytes erase command bit
bits : 5 - 5 (1 bit)

START : Send erase command to FMC bit
bits : 6 - 6 (1 bit)

LK : FMC_CTL0 lock bit
bits : 7 - 7 (1 bit)

OBWPE : Option byte erase/program enable bit
bits : 9 - 9 (1 bit)

ERIE : Error interrupt enable bit
bits : 10 - 10 (1 bit)

ENDIE : End of operation interrupt enable bit
bits : 12 - 12 (1 bit)


PID

Product ID register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID PID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : Product reserved ID code register
bits : 0 - 31 (32 bit)


ADDR0

Address register 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ADDR0 ADDR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Flash erase/program command address bits
bits : 0 - 31 (32 bit)


OBCTL

Option byte control register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OBCTL OBCTL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RERR SPC USER DATA

RERR : Option bytes read error bit
bits : 0 - 0 (1 bit)

SPC : Option bytes security protection code
bits : 1 - 1 (1 bit)

USER : Store USER of option bytes block after system reset
bits : 2 - 9 (8 bit)

DATA : Store DATA[15:0] of option bytes block after system reset
bits : 10 - 25 (16 bit)


WPR

Erase/Program Protection register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPR WPR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WP

WP : Store WP[31:0] of option bytes block after system reset
bits : 0 - 31 (32 bit)


KEY

Unlock key register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY KEY write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : FMC_CTL unlock register
bits : 0 - 31 (32 bit)


KEY1

Unlock key register 1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY1 KEY1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : FMC_CTL unlock register
bits : 0 - 31 (32 bit)


STAT1

Status register 1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT1 STAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY PGERR WPERR END

BUSY : The flash is busy bit
bits : 0 - 0 (1 bit)
access : read-only

PGERR : Program error flag bit
bits : 2 - 2 (1 bit)
access : read-write

WPERR : Erase/Program protection error flag bit
bits : 4 - 4 (1 bit)
access : read-write

END : End of operation flag bit
bits : 5 - 5 (1 bit)
access : read-write


CTL1

Control register 1
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL1 CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PG PER MER START LK ERIE ENDIE

PG : Main flash program for bank0 command bit
bits : 0 - 0 (1 bit)

PER : Main flash page erase for bank0 command bit
bits : 1 - 1 (1 bit)

MER : Main flash mass erase for bank0 command bit
bits : 2 - 2 (1 bit)

START : Send erase command to FMC bit
bits : 6 - 6 (1 bit)

LK : FMC_CTL0 lock bit
bits : 7 - 7 (1 bit)

ERIE : Error interrupt enable bit
bits : 10 - 10 (1 bit)

ENDIE : End of operation interrupt enable bit
bits : 12 - 12 (1 bit)


ADDR1

Address register 1
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ADDR1 ADDR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Flash erase/program command address bits
bits : 0 - 31 (32 bit)


OBKEY

Option byte unlock key register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OBKEY OBKEY write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OBKEY

OBKEY : FMC_ OBCTL0 option byte operation unlock register
bits : 0 - 31 (32 bit)


STAT0

Status register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT0 STAT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY PGERR WPERR END

BUSY : The flash is busy bit
bits : 0 - 0 (1 bit)
access : read-only

PGERR : Program error flag bit
bits : 2 - 2 (1 bit)
access : read-write

WPERR : Erase/Program protection error flag bit
bits : 4 - 4 (1 bit)
access : read-write

END : End of operation flag bit
bits : 5 - 5 (1 bit)
access : read-write


WSEN

Wait state enable register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WSEN WSEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WSEN

WSEN : FMC wait state enable register
bits : 0 - 0 (1 bit)



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