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USART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

STAT0

CTL1

CTL2

GP

DATA

BAUD

CTL3

RT

STAT1

CTL0


STAT0

Status register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STAT0 STAT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERR FERR NERR ORERR IDLEF RBNE TC TBE LBDF CTSF

PERR : Parity error flag
bits : 0 - 0 (1 bit)

FERR : Frame error flag
bits : 1 - 1 (1 bit)

NERR : Noise error flag
bits : 2 - 2 (1 bit)

ORERR : Overrun error
bits : 3 - 3 (1 bit)

IDLEF : IDLE frame detected flag
bits : 4 - 4 (1 bit)

RBNE : Read data buffer not empty
bits : 5 - 5 (1 bit)

TC : Transmission complete
bits : 6 - 6 (1 bit)

TBE : Transmit data buffer empty
bits : 7 - 7 (1 bit)

LBDF : LIN break detection flag
bits : 8 - 8 (1 bit)

CTSF : CTS change flag
bits : 9 - 9 (1 bit)


CTL1

Control register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL1 CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR LBLEN LBDIE CLEN CPH CPL CKEN STB LMEN

ADDR : Address of the USART
bits : 0 - 3 (4 bit)

LBLEN : LIN break frame length
bits : 5 - 5 (1 bit)

LBDIE : LIN break detection interrupt enable
bits : 6 - 6 (1 bit)

CLEN : CK Length
bits : 8 - 8 (1 bit)

CPH : Clock phase
bits : 9 - 9 (1 bit)

CPL : Clock polarity
bits : 10 - 10 (1 bit)

CKEN : CK pin enable
bits : 11 - 11 (1 bit)

STB : STOP bits length
bits : 12 - 13 (2 bit)

LMEN : LIN mode enable
bits : 14 - 14 (1 bit)


CTL2

Control register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL2 CTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRIE IREN IRLP HDEN NKEN SCEN DENR DENT RTSEN CTSEN CTSIE

ERRIE : Error interrupt enable
bits : 0 - 0 (1 bit)

IREN : IrDA mode enable
bits : 1 - 1 (1 bit)

IRLP : IrDA low-power
bits : 2 - 2 (1 bit)

HDEN : Half-duplex selection
bits : 3 - 3 (1 bit)

NKEN : Smartcard NACK enable
bits : 4 - 4 (1 bit)

SCEN : Smartcard mode enable
bits : 5 - 5 (1 bit)

DENR : DMA request enable for reception
bits : 6 - 6 (1 bit)

DENT : DMA request enable for transmission
bits : 7 - 7 (1 bit)

RTSEN : RTS enable
bits : 8 - 8 (1 bit)

CTSEN : CTS enable
bits : 9 - 9 (1 bit)

CTSIE : CTS interrupt enable
bits : 10 - 10 (1 bit)


GP

Guard time and prescaler register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP GP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC GUAT

PSC : Prescaler value
bits : 0 - 7 (8 bit)

GUAT : Guard time value in Smartcard mode
bits : 8 - 15 (8 bit)


DATA

Data register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Transmit or read data value
bits : 0 - 8 (9 bit)


BAUD

Baud rate register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BAUD BAUD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRADIV INTDIV

FRADIV : Fraction part of baud-rate divider
bits : 0 - 3 (4 bit)

INTDIV : Integer part of baud-rate divider
bits : 4 - 15 (12 bit)


CTL3

Control register 3
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL3 CTL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTEN SCRTNUM RTIE EBIE RINV TINV DINV MSBF

RTEN : Receiver timeout enable
bits : 0 - 0 (1 bit)

SCRTNUM : Smartcard auto-retry number
bits : 1 - 3 (3 bit)

RTIE : Interrupt enable bit of receive timeout event
bits : 4 - 4 (1 bit)

EBIE : Interrupt enable bit of end of block event
bits : 5 - 5 (1 bit)

RINV : RX pin level inversion
bits : 8 - 8 (1 bit)

TINV : TX pin level inversion
bits : 9 - 9 (1 bit)

DINV : Data bit level inversion
bits : 10 - 10 (1 bit)

MSBF : Most significant bit first
bits : 11 - 11 (1 bit)


RT

Receiver timeout register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RT RT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RT BL

RT : Receiver timeout threshold
bits : 0 - 23 (24 bit)

BL : Block Length
bits : 24 - 31 (8 bit)


STAT1

Status register 1
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT1 STAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTF EBF BSY

RTF : Receiver timeout flag
bits : 11 - 11 (1 bit)
access : write

EBF : End of block flag
bits : 12 - 12 (1 bit)
access : write

BSY : Busy flag
bits : 16 - 16 (1 bit)
access : read-only


CTL0

Control register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL0 CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBKCMD RWU REN TEN IDLEIE RBNEIE TCIE TBEIE PERRIE PM PCEN WM WL UEN

SBKCMD : Send break command
bits : 0 - 0 (1 bit)

RWU : Receiver wakeup from mute mode
bits : 1 - 1 (1 bit)

REN : Receiver enable
bits : 2 - 2 (1 bit)

TEN : Transmitter enable
bits : 3 - 3 (1 bit)

IDLEIE : IDLE line detected interrupt enable
bits : 4 - 4 (1 bit)

RBNEIE : Read data buffer not empty interrupt and overrun error interrupt enable
bits : 5 - 5 (1 bit)

TCIE : Transmission complete interrupt enable
bits : 6 - 6 (1 bit)

TBEIE : Transmitter buffer empty interrupt enable
bits : 7 - 7 (1 bit)

PERRIE : Parity error interrupt enable
bits : 8 - 8 (1 bit)

PM : Parity mode
bits : 9 - 9 (1 bit)

PCEN : Parity check function enable
bits : 10 - 10 (1 bit)

WM : Wakeup method in mute mode
bits : 11 - 11 (1 bit)

WL : Word length
bits : 12 - 12 (1 bit)

UEN : USART enable
bits : 13 - 13 (1 bit)



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