\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEN : DAC enable
bits : 0 - 0 (1 bit)
DBOFF : DAC output buffer disable
bits : 1 - 1 (1 bit)
DTEN : DAC trigger enable
bits : 2 - 2 (1 bit)
DTSEL : DAC trigger selection
bits : 3 - 5 (3 bit)
DWM : DAC noise wave mode
bits : 6 - 7 (2 bit)
DWBW : DAC noise wave bit width
bits : 8 - 11 (4 bit)
DDMAEN : DAC DMA enable
bits : 12 - 12 (1 bit)
DDUDRIE : DAC DMA underrun interrupt enable
bits : 13 - 13 (1 bit)
DAC 8-bit right aligned data holding register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAC_DH : DAC 8-bit right-aligned data
bits : 0 - 7 (8 bit)
DAC data output register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DAC_DO : DAC data output
bits : 0 - 11 (12 bit)
status register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DDUDR : DAC DMA underrun flag
bits : 13 - 13 (1 bit)
software trigger register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWTR : DAC software trigger
bits : 0 - 0 (1 bit)
DAC 12-bit right-aligned data holding register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAC_DH : DAC 12-bit right-aligned data
bits : 0 - 11 (12 bit)
DAC 12-bit left aligned data holding register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAC_DH : DAC 12-bit left-aligned data
bits : 4 - 15 (12 bit)
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