\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Interrupt enable register (EXTI_INTEN)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTEN0 : Enable Interrupt on line 0
bits : 0 - 0 (1 bit)
INTEN1 : Enable Interrupt on line 1
bits : 1 - 1 (1 bit)
INTEN2 : Enable Interrupt on line 2
bits : 2 - 2 (1 bit)
INTEN3 : Enable Interrupt on line 3
bits : 3 - 3 (1 bit)
INTEN4 : Enable Interrupt on line 4
bits : 4 - 4 (1 bit)
INTEN5 : Enable Interrupt on line 5
bits : 5 - 5 (1 bit)
INTEN6 : Enable Interrupt on line 6
bits : 6 - 6 (1 bit)
INTEN7 : Enable Interrupt on line 7
bits : 7 - 7 (1 bit)
INTEN8 : Enable Interrupt on line 8
bits : 8 - 8 (1 bit)
INTEN9 : Enable Interrupt on line 9
bits : 9 - 9 (1 bit)
INTEN10 : Enable Interrupt on line 10
bits : 10 - 10 (1 bit)
INTEN11 : Enable Interrupt on line 11
bits : 11 - 11 (1 bit)
INTEN12 : Enable Interrupt on line 12
bits : 12 - 12 (1 bit)
INTEN13 : Enable Interrupt on line 13
bits : 13 - 13 (1 bit)
INTEN14 : Enable Interrupt on line 14
bits : 14 - 14 (1 bit)
INTEN15 : Enable Interrupt on line 15
bits : 15 - 15 (1 bit)
INTEN16 : Enable Interrupt on line 16
bits : 16 - 16 (1 bit)
INTEN17 : Enable Interrupt on line 17
bits : 17 - 17 (1 bit)
INTEN18 : Enable Interrupt on line 18
bits : 18 - 18 (1 bit)
INTEN19 : Enable Interrupt on line 19
bits : 19 - 19 (1 bit)
INTEN20 : Enable Interrupt on line 20
bits : 20 - 20 (1 bit)
INTEN21 : Enable Interrupt on line 21
bits : 21 - 21 (1 bit)
INTEN22 : Enable Interrupt on line 22
bits : 22 - 22 (1 bit)
INTEN23 : Enable Interrupt on line 23
bits : 23 - 23 (1 bit)
INTEN24 : Enable Interrupt on line 24
bits : 24 - 24 (1 bit)
INTEN25 : Enable Interrupt on line 25
bits : 25 - 25 (1 bit)
INTEN26 : Enable Interrupt on line 26
bits : 26 - 26 (1 bit)
INTEN27 : Enable Interrupt on line 27
bits : 27 - 27 (1 bit)
Software interrupt event register (EXTI_SWIEV)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWIEV0 : Software Interrupt on line 0
bits : 0 - 0 (1 bit)
SWIEV1 : Software Interrupt on line 1
bits : 1 - 1 (1 bit)
SWIEV2 : Software Interrupt on line 2
bits : 2 - 2 (1 bit)
SWIEV3 : Software Interrupt on line 3
bits : 3 - 3 (1 bit)
SWIEV4 : Software Interrupt on line 4
bits : 4 - 4 (1 bit)
SWIEV5 : Software Interrupt on line 5
bits : 5 - 5 (1 bit)
SWIEV6 : Software Interrupt on line 6
bits : 6 - 6 (1 bit)
SWIEV7 : Software Interrupt on line 7
bits : 7 - 7 (1 bit)
SWIEV8 : Software Interrupt on line 8
bits : 8 - 8 (1 bit)
SWIEV9 : Software Interrupt on line 9
bits : 9 - 9 (1 bit)
SWIEV10 : Software Interrupt on line 10
bits : 10 - 10 (1 bit)
SWIEV11 : Software Interrupt on line 11
bits : 11 - 11 (1 bit)
SWIEV12 : Software Interrupt on line 12
bits : 12 - 12 (1 bit)
SWIEV13 : Software Interrupt on line 13
bits : 13 - 13 (1 bit)
SWIEV14 : Software Interrupt on line 14
bits : 14 - 14 (1 bit)
SWIEV15 : Software Interrupt on line 15
bits : 15 - 15 (1 bit)
SWIEV16 : Software Interrupt on line 16
bits : 16 - 16 (1 bit)
SWIEV17 : Software Interrupt on line 17
bits : 17 - 17 (1 bit)
SWIEV18 : Software Interrupt on line 18
bits : 18 - 18 (1 bit)
SWIEV19 : Software Interrupt on line 19
bits : 19 - 19 (1 bit)
SWIEV21 : Software Interrupt on line 21
bits : 21 - 21 (1 bit)
SWIEV22 : Software Interrupt on line 22
bits : 22 - 22 (1 bit)
Pending register (EXTI_PD)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD0 : Pending bit 0
bits : 0 - 0 (1 bit)
PD1 : Pending bit 1
bits : 1 - 1 (1 bit)
PD2 : Pending bit 2
bits : 2 - 2 (1 bit)
PD3 : Pending bit 3
bits : 3 - 3 (1 bit)
PD4 : Pending bit 4
bits : 4 - 4 (1 bit)
PD5 : Pending bit 5
bits : 5 - 5 (1 bit)
PD6 : Pending bit 6
bits : 6 - 6 (1 bit)
PD7 : Pending bit 7
bits : 7 - 7 (1 bit)
PD8 : Pending bit 8
bits : 8 - 8 (1 bit)
PD9 : Pending bit 9
bits : 9 - 9 (1 bit)
PD10 : Pending bit 10
bits : 10 - 10 (1 bit)
PD11 : Pending bit 11
bits : 11 - 11 (1 bit)
PD12 : Pending bit 12
bits : 12 - 12 (1 bit)
PD13 : Pending bit 13
bits : 13 - 13 (1 bit)
PD14 : Pending bit 14
bits : 14 - 14 (1 bit)
PD15 : Pending bit 15
bits : 15 - 15 (1 bit)
PD16 : Pending bit 16
bits : 16 - 16 (1 bit)
PD17 : Pending bit 17
bits : 17 - 17 (1 bit)
PD18 : Pending bit 18
bits : 18 - 18 (1 bit)
PD19 : Pending bit 19
bits : 19 - 19 (1 bit)
PD21 : Pending bit 21
bits : 21 - 21 (1 bit)
PD22 : Pending bit 22
bits : 22 - 22 (1 bit)
Event enable register (EXTI_EVEN)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVEN0 : Enable Event on line 0
bits : 0 - 0 (1 bit)
EVEN1 : Enable Event on line 1
bits : 1 - 1 (1 bit)
EVEN2 : Enable Event on line 2
bits : 2 - 2 (1 bit)
EVEN3 : Enable Event on line 3
bits : 3 - 3 (1 bit)
EVEN4 : Enable Event on line 4
bits : 4 - 4 (1 bit)
EVEN5 : Enable Event on line 5
bits : 5 - 5 (1 bit)
EVEN6 : Enable Event on line 6
bits : 6 - 6 (1 bit)
EVEN7 : Enable Event on line 7
bits : 7 - 7 (1 bit)
EVEN8 : Enable Event on line 8
bits : 8 - 8 (1 bit)
EVEN9 : Enable Event on line 9
bits : 9 - 9 (1 bit)
EVEN10 : Enable Event on line 10
bits : 10 - 10 (1 bit)
EVEN11 : Enable Event on line 11
bits : 11 - 11 (1 bit)
EVEN12 : Enable Event on line 12
bits : 12 - 12 (1 bit)
EVEN13 : Enable Event on line 13
bits : 13 - 13 (1 bit)
EVEN14 : Enable Event on line 14
bits : 14 - 14 (1 bit)
EVEN15 : Enable Event on line 15
bits : 15 - 15 (1 bit)
EVEN16 : Enable Event on line 16
bits : 16 - 16 (1 bit)
EVEN17 : Enable Event on line 17
bits : 17 - 17 (1 bit)
EVEN18 : Enable Event on line 18
bits : 18 - 18 (1 bit)
EVEN19 : Enable Event on line 19
bits : 19 - 19 (1 bit)
EVEN20 : Enable Event on line 20
bits : 20 - 20 (1 bit)
EVEN21 : Enable Event on line 21
bits : 21 - 21 (1 bit)
EVEN22 : Enable Event on line 22
bits : 22 - 22 (1 bit)
EVEN23 : Enable Event on line 23
bits : 23 - 23 (1 bit)
EVEN24 : Enable Event on line 24
bits : 24 - 24 (1 bit)
EVEN25 : Enable Event on line 25
bits : 25 - 25 (1 bit)
EVEN26 : Enable Event on line 26
bits : 26 - 26 (1 bit)
EVEN27 : Enable Event on line 27
bits : 27 - 27 (1 bit)
Rising Edge Trigger Enable register (EXTI_RTEN)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTEN0 : Rising trigger event configuration of line 0
bits : 0 - 0 (1 bit)
RTEN1 : Rising trigger event configuration of line 1
bits : 1 - 1 (1 bit)
RTEN2 : Rising trigger event configuration of line 2
bits : 2 - 2 (1 bit)
RTEN3 : Rising trigger event configuration of line 3
bits : 3 - 3 (1 bit)
RTEN4 : Rising trigger event configuration of line 4
bits : 4 - 4 (1 bit)
RTEN5 : Rising trigger event configuration of line 5
bits : 5 - 5 (1 bit)
RTEN6 : Rising trigger event configuration of line 6
bits : 6 - 6 (1 bit)
RTEN7 : Rising trigger event configuration of line 7
bits : 7 - 7 (1 bit)
RTEN8 : Rising trigger event configuration of line 8
bits : 8 - 8 (1 bit)
RTEN9 : Rising trigger event configuration of line 9
bits : 9 - 9 (1 bit)
RTEN10 : Rising trigger event configuration of line 10
bits : 10 - 10 (1 bit)
RTEN11 : Rising trigger event configuration of line 11
bits : 11 - 11 (1 bit)
RTEN12 : Rising trigger event configuration of line 12
bits : 12 - 12 (1 bit)
RTEN13 : Rising trigger event configuration of line 13
bits : 13 - 13 (1 bit)
RTEN14 : Rising trigger event configuration of line 14
bits : 14 - 14 (1 bit)
RTEN15 : Rising trigger event configuration of line 15
bits : 15 - 15 (1 bit)
RTEN16 : Rising trigger event configuration of line 16
bits : 16 - 16 (1 bit)
RTEN17 : Rising trigger event configuration of line 17
bits : 17 - 17 (1 bit)
RTEN18 : Rising trigger event configuration of line 18
bits : 18 - 18 (1 bit)
RTEN19 : Rising trigger event configuration of line 19
bits : 19 - 19 (1 bit)
RTEN21 : Rising trigger event configuration of line 21
bits : 21 - 21 (1 bit)
RTEN22 : Rising trigger event configuration of line 22
bits : 22 - 22 (1 bit)
Falling Egde Trigger Enable register (EXTI_FTEN)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTEN0 : Falling trigger event configuration of line 0
bits : 0 - 0 (1 bit)
FTEN1 : Falling trigger event configuration of line 1
bits : 1 - 1 (1 bit)
FTEN2 : Falling trigger event configuration of line 2
bits : 2 - 2 (1 bit)
FTEN3 : Falling trigger event configuration of line 3
bits : 3 - 3 (1 bit)
FTEN4 : Falling trigger event configuration of line 4
bits : 4 - 4 (1 bit)
FTEN5 : Falling trigger event configuration of line 5
bits : 5 - 5 (1 bit)
FTEN6 : Falling trigger event configuration of line 6
bits : 6 - 6 (1 bit)
FTEN7 : Falling trigger event configuration of line 7
bits : 7 - 7 (1 bit)
FTEN8 : Falling trigger event configuration of line 8
bits : 8 - 8 (1 bit)
FTEN9 : Falling trigger event configuration of line 9
bits : 9 - 9 (1 bit)
FTEN10 : Falling trigger event configuration of line 10
bits : 10 - 10 (1 bit)
FTEN11 : Falling trigger event configuration of line 11
bits : 11 - 11 (1 bit)
FTEN12 : Falling trigger event configuration of line 12
bits : 12 - 12 (1 bit)
FTEN13 : Falling trigger event configuration of line 13
bits : 13 - 13 (1 bit)
FTEN14 : Falling trigger event configuration of line 14
bits : 14 - 14 (1 bit)
FTEN15 : Falling trigger event configuration of line 15
bits : 15 - 15 (1 bit)
FTEN16 : Falling trigger event configuration of line 16
bits : 16 - 16 (1 bit)
FTEN17 : Falling trigger event configuration of line 17
bits : 17 - 17 (1 bit)
FTEN18 : Falling trigger event configuration of line 18
bits : 18 - 18 (1 bit)
FTEN19 : Falling trigger event configuration of line 19
bits : 19 - 19 (1 bit)
FTEN21 : Falling trigger event configuration of line 21
bits : 21 - 21 (1 bit)
FTEN22 : Falling trigger event configuration of line 22
bits : 22 - 22 (1 bit)
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