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I2C

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTL0

DATA

STAT0

STAT1

CKCFG

RT

CTL1

SADDR0

FMPCFG

SADDR1


CTL0

Control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL0 CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2CEN SMBEN SMBSEL ARPEN PECEN GCEN SS START STOP ACKEN POAP PECTRANS SALT SRESET

I2CEN : Peripheral enable
bits : 0 - 0 (1 bit)

SMBEN : SMBus mode
bits : 1 - 1 (1 bit)

SMBSEL : SMBus type
bits : 3 - 3 (1 bit)

ARPEN : ARP enable
bits : 4 - 4 (1 bit)

PECEN : PEC enable
bits : 5 - 5 (1 bit)

GCEN : General call enable
bits : 6 - 6 (1 bit)

SS : Clock stretching disable (Slave mode)
bits : 7 - 7 (1 bit)

START : Start generation
bits : 8 - 8 (1 bit)

STOP : Stop condition
bits : 9 - 9 (1 bit)

ACKEN : Acknowledge enable
bits : 10 - 10 (1 bit)

POAP : Acknowledge/PEC Position (for data reception)
bits : 11 - 11 (1 bit)

PECTRANS : Packet error checking
bits : 12 - 12 (1 bit)

SALT : SMBus alert
bits : 13 - 13 (1 bit)

SRESET : Software reset
bits : 15 - 15 (1 bit)


DATA

Data register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRB

TRB : Transmission or reception data buffer
bits : 0 - 7 (8 bit)


STAT0

Transfer status register 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT0 STAT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBSEND ADDSEND BTC ADD10SEND STPDET RBNE TBE BERR LOSTARB AERR OUERR PECERR SMBTO SMBALT

SBSEND : Start bit (Master mode)
bits : 0 - 0 (1 bit)
access : read-only

ADDSEND : Address sent (master mode)/matched (slave mode)
bits : 1 - 1 (1 bit)
access : read-only

BTC : Byte transmission completed
bits : 2 - 2 (1 bit)
access : read-only

ADD10SEND : Header of 10-bit address is sent in master mode
bits : 3 - 3 (1 bit)
access : read-only

STPDET : Stop detection (slave mode)
bits : 4 - 4 (1 bit)
access : read-only

RBNE : I2C_DATA is not Empty during receiving
bits : 6 - 6 (1 bit)
access : read-only

TBE : I2C_DATA is Empty during transmitting
bits : 7 - 7 (1 bit)
access : read-only

BERR : Bus error
bits : 8 - 8 (1 bit)
access : read-write

LOSTARB : Arbitration lost (master mode)
bits : 9 - 9 (1 bit)
access : read-write

AERR : Acknowledge error
bits : 10 - 10 (1 bit)
access : read-write

OUERR : Overrun/Underrun occurs in slave mode
bits : 11 - 11 (1 bit)
access : read-write

PECERR : PEC error when receiving data
bits : 12 - 12 (1 bit)
access : read-write

SMBTO : Timeout signal in SMBus mode
bits : 14 - 14 (1 bit)
access : read-write

SMBALT : SMBus alert
bits : 15 - 15 (1 bit)
access : read-write


STAT1

Transfer status register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STAT1 STAT1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASTER I2CBSY TR RXGC DEFSMB HSTSMB DUMODF PECV

MASTER : Master/slave
bits : 0 - 0 (1 bit)

I2CBSY : Bus busy
bits : 1 - 1 (1 bit)

TR : Transmitter/receiver
bits : 2 - 2 (1 bit)

RXGC : General call address (Slave mode)
bits : 4 - 4 (1 bit)

DEFSMB : SMBus device default address (Slave mode)
bits : 5 - 5 (1 bit)

HSTSMB : SMBus host header (Slave mode)
bits : 6 - 6 (1 bit)

DUMODF : Dual flag (Slave mode)
bits : 7 - 7 (1 bit)

PECV : Packet error checking register
bits : 8 - 15 (8 bit)


CKCFG

Clock configure register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKCFG CKCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKC DTCY FAST

CLKC : Clock control register in Fast/Standard mode (Master mode)
bits : 0 - 11 (12 bit)

DTCY : Fast mode duty cycle
bits : 14 - 14 (1 bit)

FAST : I2C master mode selection
bits : 15 - 15 (1 bit)


RT

Rise time register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RT RT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RISETIME

RISETIME : Maximum rise time in master mode
bits : 0 - 5 (6 bit)


CTL1

Control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL1 CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2CCLK ERRIE EVIE BUFIE DMAON DMALST

I2CCLK : Peripheral clock frequency
bits : 0 - 5 (6 bit)

ERRIE : Error interrupt enable
bits : 8 - 8 (1 bit)

EVIE : Event interrupt enable
bits : 9 - 9 (1 bit)

BUFIE : Buffer interrupt enable
bits : 10 - 10 (1 bit)

DMAON : DMA mode switch
bits : 11 - 11 (1 bit)

DMALST : Flag indicating DMA last transfer
bits : 12 - 12 (1 bit)


SADDR0

Own address register 0
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SADDR0 SADDR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS ADDFORMAT

ADDRESS : Interface address
bits : 0 - 9 (10 bit)

ADDFORMAT : Addressing mode (slave mode)
bits : 15 - 15 (1 bit)


FMPCFG

Fast-mode-plus configure register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMPCFG FMPCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMPEN

FMPEN : Fast-mode-plus enable
bits : 0 - 0 (1 bit)


SADDR1

Own address register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SADDR1 SADDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUADEN ADDRESS2

DUADEN : Dual addressing mode enable
bits : 0 - 0 (1 bit)

ADDRESS2 : Interface address
bits : 1 - 7 (7 bit)



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