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RCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTL0

APB1RST

VKEY

DSV

AHBEN

APB2EN

APB1EN

BDCTL

RSTSCK

AHBRST

CFG1

CFG2

CTL1

CFG0

INT

APB2RST

ADDCTL

ADDINT

ADDAPB1EN

ADDAPB1RST


CTL0

Control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL0 CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRC8MEN IRC8MSTB IRC8MADJ IRC8MCALIB HXTALEN HXTALSTB HXTALBPS CKMEN PLLEN PLLSTB

IRC8MEN : Internal High Speed oscillator Enable
bits : 0 - 0 (1 bit)
access : read-write

IRC8MSTB : IRC8M High Speed Internal Oscillator stabilization Flag
bits : 1 - 1 (1 bit)
access : read-only

IRC8MADJ : High Speed Internal Oscillator clock trim adjust value
bits : 3 - 7 (5 bit)
access : read-write

IRC8MCALIB : High Speed Internal Oscillator calibration value register
bits : 8 - 15 (8 bit)
access : read-only

HXTALEN : External High Speed oscillator Enable
bits : 16 - 16 (1 bit)
access : read-write

HXTALSTB : External crystal oscillator (HXTAL) clock stabilization flag
bits : 17 - 17 (1 bit)
access : read-only

HXTALBPS : External crystal oscillator (HXTAL) clock bypass mode enable
bits : 18 - 18 (1 bit)
access : read-write

CKMEN : HXTAL Clock Monitor Enable
bits : 19 - 19 (1 bit)
access : read-write

PLLEN : PLL enable
bits : 24 - 24 (1 bit)
access : read-write

PLLSTB : PLL Clock Stabilization Flag
bits : 25 - 25 (1 bit)
access : read-only


APB1RST

APB1 reset register (RCU_APB1RST)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1RST APB1RST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER1RST TIMER2RST TIMER5RST TIMER13RST WWDGTRST SPI1RST USART1RST I2C0RST I2C1RST PMURST DACRST CECRST

TIMER1RST : TIMER1 timer reset
bits : 0 - 0 (1 bit)

TIMER2RST : TIMER2 timer reset
bits : 1 - 1 (1 bit)

TIMER5RST : TIMER5 timer reset
bits : 4 - 4 (1 bit)

TIMER13RST : TIMER13 timer reset
bits : 8 - 8 (1 bit)

WWDGTRST : Window watchdog timer reset
bits : 11 - 11 (1 bit)

SPI1RST : SPI1 reset
bits : 14 - 14 (1 bit)

USART1RST : USART1 reset
bits : 17 - 17 (1 bit)

I2C0RST : I2C0 reset
bits : 21 - 21 (1 bit)

I2C1RST : I2C1 reset
bits : 22 - 22 (1 bit)

PMURST : Power control reset
bits : 28 - 28 (1 bit)

DACRST : DAC reset
bits : 29 - 29 (1 bit)

CECRST : HDMI CEC reset
bits : 30 - 30 (1 bit)


VKEY

Voltage key register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VKEY VKEY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : The key of RCU_DSV register
bits : 0 - 31 (32 bit)
access : read-write


DSV

Deep-sleep mode voltage register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSV DSV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSLPVS

DSLPVS : Deep-sleep mode voltage select
bits : 0 - 1 (2 bit)
access : read-write


AHBEN

AHB enable register (RCU_AHBEN)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBEN AHBEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAEN SRAMSPEN FMCSPEN CRCEN USBFSEN PAEN PBEN PCEN PDEN PFEN TSIEN

DMAEN : DMA clock enable
bits : 0 - 0 (1 bit)

SRAMSPEN : SRAM interface clock enable
bits : 2 - 2 (1 bit)

FMCSPEN : FMC clock enable
bits : 4 - 4 (1 bit)

CRCEN : CRC clock enable
bits : 6 - 6 (1 bit)

USBFSEN : USBFS clock enable
bits : 12 - 12 (1 bit)

PAEN : GPIO port A clock enable
bits : 17 - 17 (1 bit)

PBEN : GPIO port B clock enable
bits : 18 - 18 (1 bit)

PCEN : GPIO port C clock enable
bits : 19 - 19 (1 bit)

PDEN : GPIO port D clock enable
bits : 20 - 20 (1 bit)

PFEN : GPIO port F clock enable
bits : 22 - 22 (1 bit)

TSIEN : TSI clock enable
bits : 24 - 24 (1 bit)


APB2EN

APB2 enable register (RCU_APB2EN)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2EN APB2EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFGCMPEN ADCEN TIMER0EN SPI0EN USART0EN TIMER14EN TIMER15EN TIMER16EN

CFGCMPEN : System configuration and comparator clock enable
bits : 0 - 0 (1 bit)

ADCEN : ADC interface clock enable
bits : 9 - 9 (1 bit)

TIMER0EN : TIMER0 timer clock enable
bits : 11 - 11 (1 bit)

SPI0EN : SPI0 clock enable
bits : 12 - 12 (1 bit)

USART0EN : USART0 clock enable
bits : 14 - 14 (1 bit)

TIMER14EN : TIMER14 timer clock enable
bits : 16 - 16 (1 bit)

TIMER15EN : TIMER15 timer clock enable
bits : 17 - 17 (1 bit)

TIMER16EN : TIMER16 timer clock enable
bits : 18 - 18 (1 bit)


APB1EN

APB1 enable register (RCU_APB1EN)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1EN APB1EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER1EN TIMER2EN TIMER5EN TIMER13EN WWDGTEN SPI1EN USART1EN I2C0EN I2C1EN PMUEN DACEN CECEN

TIMER1EN : TIMER1 timer clock enable
bits : 0 - 0 (1 bit)

TIMER2EN : TIMER2 timer clock enable
bits : 1 - 1 (1 bit)

TIMER5EN : TIMER5 timer clock enable
bits : 4 - 4 (1 bit)

TIMER13EN : TIMER13 timer clock enable
bits : 8 - 8 (1 bit)

WWDGTEN : Window watchdog timer clock enable
bits : 11 - 11 (1 bit)

SPI1EN : SPI1 clock enable
bits : 14 - 14 (1 bit)

USART1EN : USART1 clock enable
bits : 17 - 17 (1 bit)

I2C0EN : I2C0 clock enable
bits : 21 - 21 (1 bit)

I2C1EN : I2C1 clock enable
bits : 22 - 22 (1 bit)

PMUEN : Power interface clock enable
bits : 28 - 28 (1 bit)

DACEN : DAC interface clock enable
bits : 29 - 29 (1 bit)

CECEN : HDMI CEC interface clock enable
bits : 30 - 30 (1 bit)


BDCTL

Backup domain control register (RCU_BDCTL)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDCTL BDCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LXTALEN LXTALSTB LXTALBPS LXTALDRI RTCSRC RTCEN BKPRST

LXTALEN : LXTAL enable
bits : 0 - 0 (1 bit)
access : read-write

LXTALSTB : External low-speed oscillator stabilization
bits : 1 - 1 (1 bit)
access : read-only

LXTALBPS : LXTAL bypass mode enable
bits : 2 - 2 (1 bit)
access : read-write

LXTALDRI : LXTAL drive capability
bits : 3 - 4 (2 bit)
access : read-write

RTCSRC : RTC clock entry selection
bits : 8 - 9 (2 bit)
access : read-write

RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)
access : read-write

BKPRST : Backup domain reset
bits : 16 - 16 (1 bit)
access : read-write


RSTSCK

Reset source /clock register (RCU_RSTSCK)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTSCK RSTSCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRC40KEN IRC40KSTB V12RSTF RSTFC OBLRSTF EPRSTF PORRSTF SWRSTF FWDGTRSTF WWDGTRSTF LPRSTF

IRC40KEN : IRC40K enable
bits : 0 - 0 (1 bit)
access : read-write

IRC40KSTB : IRC40K stabilization
bits : 1 - 1 (1 bit)
access : read-only

V12RSTF : V12 domain Power reset flag
bits : 23 - 23 (1 bit)
access : read-write

RSTFC : Reset flag clear
bits : 24 - 24 (1 bit)
access : read-write

OBLRSTF : Option byte loader reset flag
bits : 25 - 25 (1 bit)
access : read-write

EPRSTF : External PIN reset flag
bits : 26 - 26 (1 bit)
access : read-write

PORRSTF : Power reset flag
bits : 27 - 27 (1 bit)
access : read-write

SWRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-write

FWDGTRSTF : Free Watchdog timer reset flag
bits : 29 - 29 (1 bit)
access : read-write

WWDGTRSTF : Window watchdog timer reset flag
bits : 30 - 30 (1 bit)
access : read-write

LPRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
access : read-write


AHBRST

AHB reset register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBRST AHBRST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBFSRST PARST PBRST PCRST PDRST PFRST TSIRST

USBFSRST : USBFS unit reset
bits : 12 - 12 (1 bit)

PARST : GPIO port A reset
bits : 17 - 17 (1 bit)

PBRST : GPIO port B reset
bits : 18 - 18 (1 bit)

PCRST : GPIO port C reset
bits : 19 - 19 (1 bit)

PDRST : GPIO port D reset
bits : 20 - 20 (1 bit)

PFRST : GPIO port F reset
bits : 22 - 22 (1 bit)

TSIRST : TSI unit reset
bits : 24 - 24 (1 bit)


CFG1

Configuration register 1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG1 CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREDV PLLPRESEL PLLMF

PREDV : CK_HXTAL or CK_IRC48M divider previous PLL
bits : 0 - 3 (4 bit)

PLLPRESEL : PLL clock source preselection
bits : 30 - 30 (1 bit)

PLLMF : Bit 5 of PLLMF
bits : 31 - 31 (1 bit)


CFG2

Configuration register 2
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG2 CFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART0SEL CECSEL ADCSEL IRC28MDIV USBFSPSC ADCPSC

USART0SEL : CK_USART0 clock source selection
bits : 0 - 1 (2 bit)

CECSEL : CK_CEC clock source selection
bits : 6 - 6 (1 bit)

ADCSEL : CK_ADC clock source selection
bits : 8 - 8 (1 bit)

IRC28MDIV : CK_IRC28M divider 2 or not
bits : 16 - 16 (1 bit)

USBFSPSC : Bit 2 of USBFSPSC
bits : 30 - 30 (1 bit)

ADCPSC : Bit 2 of ADCPSC
bits : 31 - 31 (1 bit)


CTL1

Control register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL1 CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRC28MEN IRC28MSTB IRC28MADJ IRC28MCALIB

IRC28MEN : IRC28M Internal 28M RC oscillator Enable
bits : 0 - 0 (1 bit)
access : read-write

IRC28MSTB : IRC28M Internal 28M RC Oscillator stabilization Flag
bits : 1 - 1 (1 bit)
access : read-only

IRC28MADJ : Internal 28M RC Oscillator clock trim adjust value
bits : 3 - 7 (5 bit)
access : read-write

IRC28MCALIB : Internal 28M RC Oscillator calibration value register
bits : 8 - 15 (8 bit)
access : read-only


CFG0

Clock configuration register 0 (RCU_CFG0)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG0 CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCS SCSS AHBPSC APB1PSC APB2PSC ADCPSC PLLSEL PLLPREDV PLLMF USBFSPSC CKOUTSEL PLLMF_MSB CKOUTDIV PLLDV

SCS : System clock switch
bits : 0 - 1 (2 bit)
access : read-write

SCSS : System clock switch status
bits : 2 - 3 (2 bit)
access : read-only

AHBPSC : AHB prescaler selection
bits : 4 - 7 (4 bit)
access : read-write

APB1PSC : APB1 prescaler selection
bits : 8 - 10 (3 bit)
access : read-write

APB2PSC : APB2 prescaler selection
bits : 11 - 13 (3 bit)
access : read-write

ADCPSC : ADC clock prescaler selection
bits : 14 - 15 (2 bit)
access : read-write

PLLSEL : PLL Clock Source Selection
bits : 16 - 16 (1 bit)
access : read-write

PLLPREDV : HXTAL divider for PLL source clock selection.
bits : 17 - 17 (1 bit)
access : read-write

PLLMF : PLL multiply factor
bits : 18 - 21 (4 bit)
access : read-write

USBFSPSC : USBFS clock prescaler selection
bits : 22 - 23 (2 bit)
access : read-write

CKOUTSEL : CK_OUT Clock Source Selection
bits : 24 - 26 (3 bit)
access : read-write

PLLMF_MSB : Bit 4 of PLLMF register
bits : 27 - 27 (1 bit)
access : read-write

CKOUTDIV : The CK_OUT divider which the CK_OUT frequency can be reduced
bits : 28 - 30 (3 bit)
access : read-write

PLLDV : The CK_PLL divide by 1 or 2 for CK_OUT
bits : 31 - 31 (1 bit)
access : read-write


INT

Clock interrupt register (RCU_INT)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRC40KSTBIF LXTALSTBIF IRC8MSTBIF HXTALSTBIF PLLSTBIF IRC28MSTBIF CKMIF IRC40KSTBIE LXTALSTBIE IRC8MSTBIE HXTALSTBIE PLLSTBIE IRC28MSTBIE IRC40KSTBIC LXTALSTBIC IRC8MSTBIC HXTALSTBIC PLLSTBIC IRC28MSTBIC CKMIC

IRC40KSTBIF : IRC40K stabilization interrupt flag
bits : 0 - 0 (1 bit)
access : read-only

LXTALSTBIF : LXTAL stabilization interrupt flag
bits : 1 - 1 (1 bit)
access : read-only

IRC8MSTBIF : IRC8M stabilization interrupt flag
bits : 2 - 2 (1 bit)
access : read-only

HXTALSTBIF : HXTAL stabilization interrupt flag
bits : 3 - 3 (1 bit)
access : read-only

PLLSTBIF : PLL stabilization interrupt flag
bits : 4 - 4 (1 bit)
access : read-only

IRC28MSTBIF : IRC28M stabilization interrupt flag
bits : 5 - 5 (1 bit)
access : read-only

CKMIF : HXTAL Clock Stuck Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-only

IRC40KSTBIE : IRC40K Stabilization interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

LXTALSTBIE : LXTAL Stabilization Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

IRC8MSTBIE : IRC8M Stabilization Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

HXTALSTBIE : HXTAL Stabilization Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

PLLSTBIE : PLL Stabilization Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write

IRC28MSTBIE : IRC28M Stabilization Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write

IRC40KSTBIC : IRC40K Stabilization Interrupt Clear
bits : 16 - 16 (1 bit)
access : write-only

LXTALSTBIC : LXTAL Stabilization Interrupt Clear
bits : 17 - 17 (1 bit)
access : write-only

IRC8MSTBIC : IRC8M Stabilization Interrupt Clear
bits : 18 - 18 (1 bit)
access : write-only

HXTALSTBIC : HXTAL Stabilization Interrupt Clear
bits : 19 - 19 (1 bit)
access : write-only

PLLSTBIC : PLL stabilization Interrupt Clear
bits : 20 - 20 (1 bit)
access : write-only

IRC28MSTBIC : IRC28M stabilization Interrupt Clear
bits : 21 - 21 (1 bit)
access : write-only

CKMIC : HXTAL Clock Stuck Interrupt Clear
bits : 23 - 23 (1 bit)
access : write-only


APB2RST

APB2 reset register (RCU_APB2RST)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2RST APB2RST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFGCMPRST ADCRST TIMER0RST SPI0RST USART0RST TIMER14RST TIMER15RST TIMER16RST

CFGCMPRST : System configuration and comparator reset
bits : 0 - 0 (1 bit)

ADCRST : ADC reset
bits : 9 - 9 (1 bit)

TIMER0RST : TIMER0 reset
bits : 11 - 11 (1 bit)

SPI0RST : SPI0 Reset
bits : 12 - 12 (1 bit)

USART0RST : USART0 Reset
bits : 14 - 14 (1 bit)

TIMER14RST : TIMER14 reset
bits : 16 - 16 (1 bit)

TIMER15RST : TIMER15 reset
bits : 17 - 17 (1 bit)

TIMER16RST : TIMER16 reset
bits : 18 - 18 (1 bit)


ADDCTL

Additional clock control register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDCTL ADDCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CK48MSEL IRC48MEN IRC48MSTB IRC48MCALIB

CK48MSEL : 48MHz clock selection
bits : 0 - 0 (1 bit)
access : read-write

IRC48MEN : Internal 48MHz RC oscillator enable
bits : 16 - 16 (1 bit)
access : read-write

IRC48MSTB : Internal 48MHz RC oscillator clock stabilization Flag
bits : 17 - 17 (1 bit)
access : read-write

IRC48MCALIB : Internal 48MHz RC oscillator calibration value register
bits : 24 - 31 (8 bit)
access : read-write


ADDINT

Additional clock interrupt register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDINT ADDINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRC48MSTBIF IRC48MSTBIE IRC48MSTBIC

IRC48MSTBIF : IRC48M stabilization interrupt flag
bits : 6 - 6 (1 bit)
access : read-only

IRC48MSTBIE : Internal 48 MHz RC oscillator Stabilization Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write

IRC48MSTBIC : Internal 48 MHz RC oscillator Stabilization Interrupt Clear
bits : 22 - 22 (1 bit)
access : read-write


ADDAPB1EN

APB1 additional enable register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDAPB1EN ADDAPB1EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTCEN

CTCEN : CTC clock enable
bits : 27 - 27 (1 bit)
access : read-write


ADDAPB1RST

APB1 additional reset register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDAPB1RST ADDAPB1RST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTCRST

CTCRST : CTC reset
bits : 27 - 27 (1 bit)
access : read-write



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