\n

SPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTL0

CPCPOLY

RCRC

TCRC

I2SCTL

I2SPSC

CTL1

STAT

QCTL

DATA


CTL0

control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL0 CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKPH CKPL MSTMOD PSC SPIEN LF SWNSS SWNSSEN RO FF16 CRCNT CRCEN BDOEN BDEN

CKPH : Clock Phase Selection
bits : 0 - 0 (1 bit)

CKPL : Clock Polarity Selection
bits : 1 - 1 (1 bit)

MSTMOD : Master Mode Enable
bits : 2 - 2 (1 bit)

PSC : Master Clock Prescaler Selection
bits : 3 - 5 (3 bit)

SPIEN : SPI enable
bits : 6 - 6 (1 bit)

LF : LSB First Mode
bits : 7 - 7 (1 bit)

SWNSS : NSS Pin Selection In NSS Software Mode
bits : 8 - 8 (1 bit)

SWNSSEN : NSS Software Mode Selection
bits : 9 - 9 (1 bit)

RO : Receive only
bits : 10 - 10 (1 bit)

FF16 : Data frame format
bits : 11 - 11 (1 bit)

CRCNT : CRC transfer next
bits : 12 - 12 (1 bit)

CRCEN : Hardware CRC calculation enable
bits : 13 - 13 (1 bit)

BDOEN : Bidirectional Transmit output enable
bits : 14 - 14 (1 bit)

BDEN : Bidirectional enable
bits : 15 - 15 (1 bit)


CPCPOLY

CRC polynomial register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPCPOLY CPCPOLY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPR

CPR : CRC polynomial register
bits : 0 - 15 (16 bit)


RCRC

RX CRC register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RCRC RCRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCR

RCR : RX RCR register
bits : 0 - 15 (16 bit)


TCRC

TX CRC register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TCRC TCRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCR

TCR : Tx CRC register
bits : 0 - 15 (16 bit)


I2SCTL

I2S configuration register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2SCTL I2SCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHLEN DTLEN CKPL I2SSTD PCMSMOD I2SOPMOD I2SEN I2SSEL

CHLEN : Channel length (number of bits per audio channel)
bits : 0 - 0 (1 bit)

DTLEN : Data length to be transferred
bits : 1 - 2 (2 bit)

CKPL : Idle state clock polarity
bits : 3 - 3 (1 bit)

I2SSTD : I2S standard selection
bits : 4 - 5 (2 bit)

PCMSMOD : PCM frame synchronization
bits : 7 - 7 (1 bit)

I2SOPMOD : I2S configuration mode
bits : 8 - 9 (2 bit)

I2SEN : I2S Enable
bits : 10 - 10 (1 bit)

I2SSEL : I2S mode selection
bits : 11 - 11 (1 bit)


I2SPSC

I2S prescaler register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2SPSC I2SPSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV OF MCKOEN

DIV : Dividing factor for the prescaler
bits : 0 - 7 (8 bit)

OF : Odd factor for the prescaler
bits : 8 - 8 (1 bit)

MCKOEN : I2S_MCK output enable
bits : 9 - 9 (1 bit)


CTL1

control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL1 CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREN DMATEN NSSDRV NSSP TMOD ERRIE RBNEIE TBEIE

DMAREN : Rx buffer DMA enable
bits : 0 - 0 (1 bit)

DMATEN : Tx buffer DMA enable
bits : 1 - 1 (1 bit)

NSSDRV : NSS output enable
bits : 2 - 2 (1 bit)

NSSP : SPI NSS Pulse Mode Enable
bits : 3 - 3 (1 bit)

TMOD : SPI TI Mode Enable
bits : 4 - 4 (1 bit)

ERRIE : Error interrupt enable
bits : 5 - 5 (1 bit)

RBNEIE : Receive Buffer Not Empty Interrupt Enable
bits : 6 - 6 (1 bit)

TBEIE : Transmit Buffer Empty Interrupt Enable
bits : 7 - 7 (1 bit)


STAT

status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RBNE TBE I2SCH TXURERR CRCERR CONFERR RXORERR TRANS FERR

RBNE : Receive Buffer Not Empty
bits : 0 - 0 (1 bit)
access : read-only

TBE : Transmit Buffer Empty
bits : 1 - 1 (1 bit)
access : read-only

I2SCH : I2S channel side
bits : 2 - 2 (1 bit)
access : read-only

TXURERR : Transmission underrun error bit
bits : 3 - 3 (1 bit)
access : read-only

CRCERR : SPI CRC Error Bit
bits : 4 - 4 (1 bit)
access : read-write

CONFERR : SPI Configuration error
bits : 5 - 5 (1 bit)
access : read-only

RXORERR : Reception Overrun Error Bit
bits : 6 - 6 (1 bit)
access : read-only

TRANS : Transmitting On-going Bit
bits : 7 - 7 (1 bit)
access : read-only

FERR : Format Error
bits : 8 - 8 (1 bit)
access : read-only


QCTL

SPI quad wird control register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QCTL QCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMOD QRD IO23_DRV

QMOD : Quad wire mode enable
bits : 0 - 0 (1 bit)

QRD : Quad wire read select
bits : 1 - 1 (1 bit)

IO23_DRV : Drive IO2 and IO3 enable
bits : 2 - 2 (1 bit)


DATA

data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data register
bits : 0 - 15 (16 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.