\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Counter enable
bits : 0 - 0 (1 bit)
UPDIS : Update disable
bits : 1 - 1 (1 bit)
UPS : Update request source
bits : 2 - 2 (1 bit)
SPM : One-pulse mode
bits : 3 - 3 (1 bit)
DIR : Direction
bits : 4 - 4 (1 bit)
CAM : Center-aligned mode selection
bits : 5 - 6 (2 bit)
ARSE : Auto-reload preload enable
bits : 7 - 7 (1 bit)
CKDIV : Clock division
bits : 8 - 9 (2 bit)
interrupt flag register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPIF : Update interrupt flag
bits : 0 - 0 (1 bit)
CH0IF : Capture/compare 0 interrupt flag
bits : 1 - 1 (1 bit)
CH1IF : Capture/Compare 1 interrupt flag
bits : 2 - 2 (1 bit)
CH2IF : Capture/Compare 2 interrupt flag
bits : 3 - 3 (1 bit)
CH3IF : Capture/Compare 3 interrupt flag
bits : 4 - 4 (1 bit)
TRGIF : Trigger interrupt flag
bits : 6 - 6 (1 bit)
CH0OF : Capture/Compare 0 overcapture flag
bits : 9 - 9 (1 bit)
CH1OF : Capture/compare 1 overcapture flag
bits : 10 - 10 (1 bit)
CH2OF : Capture/Compare 2 overcapture flag
bits : 11 - 11 (1 bit)
CH3OF : Capture/Compare 3 overcapture flag
bits : 12 - 12 (1 bit)
event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UPG : Update generation
bits : 0 - 0 (1 bit)
CH0G : Capture/compare 0 generation
bits : 1 - 1 (1 bit)
CH1G : Capture/compare 1 generation
bits : 2 - 2 (1 bit)
CH2G : Capture/compare 2 generation
bits : 3 - 3 (1 bit)
CH3G : Capture/compare 3 generation
bits : 4 - 4 (1 bit)
TRGG : Trigger generation
bits : 6 - 6 (1 bit)
capture/compare mode register 0 (output mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0MS : Capture/Compare 0 selection
bits : 0 - 1 (2 bit)
CH0COMFEN : Output compare 0 fast enable
bits : 2 - 2 (1 bit)
CH0COMSEN : Output compare 0 preload enable
bits : 3 - 3 (1 bit)
CH0COMCTL : Output compare 0 mode
bits : 4 - 6 (3 bit)
CH0COMCEN : Output compare 0 clear enable
bits : 7 - 7 (1 bit)
CH1MS : Capture/Compare 1 selection
bits : 8 - 9 (2 bit)
CH1COMFEN : Output compare 1 fast enable
bits : 10 - 10 (1 bit)
CH1COMSEN : Output compare 1 preload enable
bits : 11 - 11 (1 bit)
CH1COMCTL : Output compare 1 mode
bits : 12 - 14 (3 bit)
CH1COMCEN : Output compare 1 clear enable
bits : 15 - 15 (1 bit)
capture/compare mode register 0 (input mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CHCTL0_Output
reset_Mask : 0x0
CH0MS : Capture/Compare 0 selection
bits : 0 - 1 (2 bit)
CH0CAPPSC : Input capture 0 prescaler
bits : 2 - 3 (2 bit)
CH0CAPFLT : Input capture 0 filter
bits : 4 - 7 (4 bit)
CH1MS : Capture/compare 1 selection
bits : 8 - 9 (2 bit)
CH1CAPPSC : Input capture 1 prescaler
bits : 10 - 11 (2 bit)
CH1CAPFLT : Input capture 1 filter
bits : 12 - 15 (4 bit)
capture/compare mode register 1 (output mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2MS : Capture/Compare 2 selection
bits : 0 - 1 (2 bit)
CH2COMFEN : Output compare 2 fast enable
bits : 2 - 2 (1 bit)
CH2COMSEN : Output compare 2 preload enable
bits : 3 - 3 (1 bit)
CH2COMCTL : Output compare 2 mode
bits : 4 - 6 (3 bit)
CH2COMCEN : Output compare 2 clear enable
bits : 7 - 7 (1 bit)
CH3MS : Capture/Compare 3 selection
bits : 8 - 9 (2 bit)
CH3COMFEN : Output compare 3 fast enable
bits : 10 - 10 (1 bit)
CH3COMSEN : Output compare 3 preload enable
bits : 11 - 11 (1 bit)
CH3COMCTL : Output compare 3 mode
bits : 12 - 14 (3 bit)
CH3COMCEN : Output compare 3 clear enable
bits : 15 - 15 (1 bit)
capture/compare mode register 1 (input mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CHCTL1_Output
reset_Mask : 0x0
CH2MS : Capture/Compare 2 selection
bits : 0 - 1 (2 bit)
CH2CAPPSC : Input capture 2 prescaler
bits : 2 - 3 (2 bit)
CH2CAPFLT : Input capture 2 filter
bits : 4 - 7 (4 bit)
CH3MS : Capture/Compare 3 selection
bits : 8 - 9 (2 bit)
CH3CAPPSC : Input capture 3 prescaler
bits : 10 - 11 (2 bit)
CH3CAPFLT : Input capture 3 filter
bits : 12 - 15 (4 bit)
capture/compare enable register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0EN : Capture/Compare 0 output enable
bits : 0 - 0 (1 bit)
CH0P : Capture/Compare 0 output Polarity
bits : 1 - 1 (1 bit)
CH0NP : Capture/Compare 0 output Polarity
bits : 3 - 3 (1 bit)
CH1EN : Capture/Compare 1 output enable
bits : 4 - 4 (1 bit)
CH1P : Capture/Compare 1 output Polarity
bits : 5 - 5 (1 bit)
CH1NP : Capture/Compare 1 output Polarity
bits : 7 - 7 (1 bit)
CH2EN : Capture/Compare 2 output enable
bits : 8 - 8 (1 bit)
CH2P : Capture/Compare 2 output Polarity
bits : 9 - 9 (1 bit)
CH2NP : Capture/Compare 2 output Polarity
bits : 11 - 11 (1 bit)
CH3EN : Capture/Compare 3 output enable
bits : 12 - 12 (1 bit)
CH3P : Capture/Compare 3 output Polarity
bits : 13 - 13 (1 bit)
CH3NP : Capture/Compare 3 output Polarity
bits : 15 - 15 (1 bit)
counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : counter value
bits : 0 - 31 (32 bit)
prescaler
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : Prescaler value
bits : 0 - 15 (16 bit)
auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CARL : Low Auto-reload value
bits : 0 - 31 (32 bit)
capture/compare register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0VAL : Low Capture/Compare 1 value
bits : 0 - 31 (32 bit)
capture/compare register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1VAL : Low Capture/Compare 2 value
bits : 0 - 31 (32 bit)
capture/compare register 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2VAL : High Capture/Compare value (TIM2 only)
bits : 0 - 31 (32 bit)
control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAS : Capture/compare DMA selection
bits : 3 - 3 (1 bit)
MMC : Master mode selection
bits : 4 - 6 (3 bit)
TI0S : TI0 selection
bits : 7 - 7 (1 bit)
capture/compare register 3
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3VAL : High Capture/Compare value (TIM2 only)
bits : 0 - 31 (32 bit)
DMA control register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMATA : DMA base address
bits : 0 - 4 (5 bit)
DMATC : DMA burst length
bits : 8 - 12 (5 bit)
DMA address for full transfer
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMATB : DMA register for burst accesses
bits : 0 - 15 (16 bit)
slave mode control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMC : Slave mode selection
bits : 0 - 2 (3 bit)
OCRC : OCREF clear source selection
bits : 3 - 3 (1 bit)
TRGS : Trigger selection
bits : 4 - 6 (3 bit)
MSM : Master/Slave mode
bits : 7 - 7 (1 bit)
ETFC : External trigger filter
bits : 8 - 11 (4 bit)
ETPSC : External trigger prescaler
bits : 12 - 13 (2 bit)
SMC1 : External clock enable
bits : 14 - 14 (1 bit)
ETP : External trigger polarity
bits : 15 - 15 (1 bit)
DMA/Interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPIE : Update interrupt enable
bits : 0 - 0 (1 bit)
CH0IE : Capture/Compare 0 interrupt enable
bits : 1 - 1 (1 bit)
CH1IE : Capture/Compare 1 interrupt enable
bits : 2 - 2 (1 bit)
CH2IE : Capture/Compare 2 interrupt enable
bits : 3 - 3 (1 bit)
CH3IE : Capture/Compare 3 interrupt enable
bits : 4 - 4 (1 bit)
TRGIE : Trigger interrupt enable
bits : 6 - 6 (1 bit)
UPDEN : Update DMA request enable
bits : 8 - 8 (1 bit)
CH0DEN : Capture/Compare 1 DMA request enable
bits : 9 - 9 (1 bit)
CH1DEN : Capture/Compare 1 DMA request enable
bits : 10 - 10 (1 bit)
CH2DEN : Capture/Compare 2 DMA request enable
bits : 11 - 11 (1 bit)
CH3DEN : Capture/Compare 3 DMA request enable
bits : 12 - 12 (1 bit)
TRGDEN : Trigger DMA request enable
bits : 14 - 14 (1 bit)
Configuration
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHVSEL : Write CHxVAL register selection
bits : 1 - 1 (1 bit)
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