\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Counter enable
bits : 0 - 0 (1 bit)
UPDIS : Update disable
bits : 1 - 1 (1 bit)
UPS : Update request source
bits : 2 - 2 (1 bit)
ARSE : Auto-reload preload enable
bits : 7 - 7 (1 bit)
CKDIV : Clock division
bits : 8 - 9 (2 bit)
interrupt flag register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPIF : Update interrupt flag
bits : 0 - 0 (1 bit)
CH0IF : Capture/compare 0 interrupt flag
bits : 1 - 1 (1 bit)
CH0OF : Capture/Compare 0 overcapture flag
bits : 9 - 9 (1 bit)
event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UPG : Update generation
bits : 0 - 0 (1 bit)
CH0G : Capture/compare 0 generation
bits : 1 - 1 (1 bit)
capture/compare mode register (output mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0MS : Capture/Compare 0 selection
bits : 0 - 1 (2 bit)
CH0COMFEN : Output compare 0 fast enable
bits : 2 - 2 (1 bit)
CH0COMSEN : Output Compare 0 preload enable
bits : 3 - 3 (1 bit)
CH0COMCTL : Output Compare 0 mode
bits : 4 - 6 (3 bit)
capture/compare mode register (input mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CHCTL0_Output
reset_Mask : 0x0
CH0MS : Capture/Compare 0 selection
bits : 0 - 1 (2 bit)
CH0CAPPSC : Input capture 0 prescaler
bits : 2 - 3 (2 bit)
CH0CAPFLT : Input capture 0 filter
bits : 4 - 7 (4 bit)
capture/compare enable register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0EN : Capture/Compare 1 output enable
bits : 0 - 0 (1 bit)
CH0P : Capture/Compare 0 output Polarity
bits : 1 - 1 (1 bit)
CH0NP : Capture/Compare 0 output Polarity
bits : 3 - 3 (1 bit)
counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : counter value
bits : 0 - 15 (16 bit)
prescaler
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : Prescaler value
bits : 0 - 15 (16 bit)
auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CARL : Auto-reload value
bits : 0 - 15 (16 bit)
capture/compare register 0
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0VAL : Capture/Compare 1 value
bits : 0 - 15 (16 bit)
channel input remap register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CI0_RMP : Timer input 0 remap
bits : 0 - 1 (2 bit)
DMA/Interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPIE : Update interrupt enable
bits : 0 - 0 (1 bit)
CH0IE : Capture/Compare 0 interrupt enable
bits : 1 - 1 (1 bit)
configuration register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHVSEL : Write CHxVAL register selection
bits : 1 - 1 (1 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.