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TIMER

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTL0

INTF

SWEVG

CHCTL0_Output

CHCTL0_Input

CHCTL2

CNT

PSC

CAR

CREP

CH0CV

CTL1

CCHP

DMACFG

DMATB

DMAINTEN

CFG


CTL0

control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL0 CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN UPDIS UPS SPM ARSE CKDIV

CEN : Counter enable
bits : 0 - 0 (1 bit)

UPDIS : Update disable
bits : 1 - 1 (1 bit)

UPS : Update request source
bits : 2 - 2 (1 bit)

SPM : One-pulse mode
bits : 3 - 3 (1 bit)

ARSE : Auto-reload preload enable
bits : 7 - 7 (1 bit)

CKDIV : Clock division
bits : 8 - 9 (2 bit)


INTF

interrupt flag register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTF INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPIF CH0IF CMTIF BRKIF CH0OF

UPIF : Update interrupt flag
bits : 0 - 0 (1 bit)

CH0IF : Capture/compare 0 interrupt flag
bits : 1 - 1 (1 bit)

CMTIF : COM interrupt flag
bits : 5 - 5 (1 bit)

BRKIF : Break interrupt flag
bits : 7 - 7 (1 bit)

CH0OF : Capture/Compare 0 overcapture flag
bits : 9 - 9 (1 bit)


SWEVG

event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWEVG SWEVG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPG CH0G CMTG BRKG

UPG : Update generation
bits : 0 - 0 (1 bit)

CH0G : Capture/compare 0 generation
bits : 1 - 1 (1 bit)

CMTG : Capture/Compare control update generation
bits : 5 - 5 (1 bit)

BRKG : Break generation
bits : 7 - 7 (1 bit)


CHCTL0_Output

capture/compare mode register (output mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTL0_Output CHCTL0_Output read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0MS CH0COMFEN CH0COMSEN CH0COMCTL

CH0MS : Capture/Compare 0 selection
bits : 0 - 1 (2 bit)

CH0COMFEN : Output Compare 0 fast enable
bits : 2 - 2 (1 bit)

CH0COMSEN : Output Compare 0 preload enable
bits : 3 - 3 (1 bit)

CH0COMCTL : Output Compare 0 mode
bits : 4 - 6 (3 bit)


CHCTL0_Input

capture/compare mode register 0 (input mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CHCTL0_Output
reset_Mask : 0x0

CHCTL0_Input CHCTL0_Input read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0MS CH0CAPPSC CH0CAPFLT

CH0MS : Capture/Compare 0 selection
bits : 0 - 1 (2 bit)

CH0CAPPSC : Input capture 0 prescaler
bits : 2 - 3 (2 bit)

CH0CAPFLT : Input capture 0 filter
bits : 4 - 7 (4 bit)


CHCTL2

capture/compare enable register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTL2 CHCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0EN CH0P CH0NEN CH0NP

CH0EN : Capture/Compare 0 output enable
bits : 0 - 0 (1 bit)

CH0P : Capture/Compare 0 output Polarity
bits : 1 - 1 (1 bit)

CH0NEN : Capture/Compare 0 complementary output enable
bits : 2 - 2 (1 bit)

CH0NP : Capture/Compare 0 output Polarity
bits : 3 - 3 (1 bit)


CNT

counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : counter value
bits : 0 - 15 (16 bit)


PSC

prescaler
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSC PSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC

PSC : Prescaler value
bits : 0 - 15 (16 bit)


CAR

auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAR CAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARL

CARL : Auto-reload value
bits : 0 - 15 (16 bit)


CREP

repetition counter register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CREP CREP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CREP

CREP : Repetition counter value
bits : 0 - 7 (8 bit)


CH0CV

capture/compare register 0
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0CV CH0CV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0VAL

CH0VAL : Capture/Compare 0 value
bits : 0 - 15 (16 bit)


CTL1

control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL1 CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCSE CCUC DMAS ISO0 ISO0N

CCSE : Capture/compare preloaded control
bits : 0 - 0 (1 bit)

CCUC : Capture/compare control update selection
bits : 2 - 2 (1 bit)

DMAS : Capture/compare DMA selection
bits : 3 - 3 (1 bit)

ISO0 : Output Idle state 0
bits : 8 - 8 (1 bit)

ISO0N : Output Idle state 0
bits : 9 - 9 (1 bit)


CCHP

break and dead-time register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCHP CCHP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCFG PROT IOS ROS BRKEN BRKP OAEN POEN

DTCFG : Dead-time generator setup
bits : 0 - 7 (8 bit)

PROT : complementary register protect control
bits : 8 - 9 (2 bit)

IOS : Off-state selection for Idle mode
bits : 10 - 10 (1 bit)

ROS : Off-state selection for Run mode
bits : 11 - 11 (1 bit)

BRKEN : Break enable
bits : 12 - 12 (1 bit)

BRKP : Break polarity
bits : 13 - 13 (1 bit)

OAEN : Automatic output enable
bits : 14 - 14 (1 bit)

POEN : Main output enable
bits : 15 - 15 (1 bit)


DMACFG

DMA configuration register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACFG DMACFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMATA DMATC

DMATA : DMA transfer access start address
bits : 0 - 4 (5 bit)

DMATC : DMA transfer count
bits : 8 - 12 (5 bit)


DMATB

DMA transfer buffer register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMATB DMATB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMATB

DMATB : DMA register for burst accesses
bits : 0 - 15 (16 bit)


DMAINTEN

DMA/Interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAINTEN DMAINTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPIE CH0IE CMTIE BRKIE UPDEN CH0DEN

UPIE : Update interrupt enable
bits : 0 - 0 (1 bit)

CH0IE : Capture/Compare 0 interrupt enable
bits : 1 - 1 (1 bit)

CMTIE : COM interrupt enable
bits : 5 - 5 (1 bit)

BRKIE : Break interrupt enable
bits : 7 - 7 (1 bit)

UPDEN : Update DMA request enable
bits : 8 - 8 (1 bit)

CH0DEN : Capture/Compare 0 DMA request enable
bits : 9 - 9 (1 bit)


CFG

configuration register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTSEL CHVSEL

OUTSEL : The output value selection
bits : 0 - 0 (1 bit)

CHVSEL : Write CHxVAL register selection
bits : 1 - 1 (1 bit)



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