\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSIEN : Touch sensing controller enable
bits : 0 - 0 (1 bit)
TSIS : Start a new acquisition
bits : 1 - 1 (1 bit)
TRGMOD : Trigger mode selection
bits : 2 - 2 (1 bit)
EGSEL : Edge selection
bits : 3 - 3 (1 bit)
PINMOD : I/O Default mode
bits : 4 - 4 (1 bit)
MCN : Max count value
bits : 5 - 7 (3 bit)
CTCDIV : pulse generator prescaler
bits : 12 - 14 (3 bit)
ECDIV : Spread spectrum prescaler
bits : 15 - 15 (1 bit)
ECEN : Spread spectrum enable
bits : 16 - 16 (1 bit)
ECDT : Spread spectrum deviation
bits : 17 - 23 (7 bit)
CTDT : Charge transfer pulse low
bits : 24 - 27 (4 bit)
CDT : Charge transfer pulse high
bits : 28 - 31 (4 bit)
Pin hysteresis mode register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
G0P0 : G0P0 Schmitt trigger hysteresis mode
bits : 0 - 0 (1 bit)
G0P1 : G0P1 Schmitt trigger hysteresis mode
bits : 1 - 1 (1 bit)
G0P2 : G0P2 Schmitt trigger hysteresis mode
bits : 2 - 2 (1 bit)
G0P3 : G0P3 Schmitt trigger hysteresis mode
bits : 3 - 3 (1 bit)
G1P0 : G1P0 Schmitt trigger hysteresis mode
bits : 4 - 4 (1 bit)
G1P1 : G1P1 Schmitt trigger hysteresis mode
bits : 5 - 5 (1 bit)
G1P2 : G1P2 Schmitt trigger hysteresis mode
bits : 6 - 6 (1 bit)
G1P3 : G1P3 Schmitt trigger hysteresis mode
bits : 7 - 7 (1 bit)
G2P0 : G2P0 Schmitt trigger hysteresis mode
bits : 8 - 8 (1 bit)
G2P1 : G2P1 Schmitt trigger hysteresis mode
bits : 9 - 9 (1 bit)
G2P2 : G2P2 Schmitt trigger hysteresis mode
bits : 10 - 10 (1 bit)
G2P3 : G2P3 Schmitt trigger hysteresis mode
bits : 11 - 11 (1 bit)
G3P0 : G3P0 Schmitt trigger hysteresis mode
bits : 12 - 12 (1 bit)
G3P1 : G3P1 Schmitt trigger hysteresis mode
bits : 13 - 13 (1 bit)
G3P2 : G3P2 Schmitt trigger hysteresis mode
bits : 14 - 14 (1 bit)
G3P3 : G3P3 Schmitt trigger hysteresis mode
bits : 15 - 15 (1 bit)
G4P0 : G4P0 Schmitt trigger hysteresis mode
bits : 16 - 16 (1 bit)
G4P1 : G4P1 Schmitt trigger hysteresis mode
bits : 17 - 17 (1 bit)
G4P2 : G4P2 Schmitt trigger hysteresis mode
bits : 18 - 18 (1 bit)
G4P3 : G4P3 Schmitt trigger hysteresis mode
bits : 19 - 19 (1 bit)
G5P0 : G5P0 Schmitt trigger hysteresis mode
bits : 20 - 20 (1 bit)
G5P1 : G5P1 Schmitt trigger hysteresis mode
bits : 21 - 21 (1 bit)
G5P2 : G5P2 Schmitt trigger hysteresis mode
bits : 22 - 22 (1 bit)
G5P3 : G5P3 Schmitt trigger hysteresis mode
bits : 23 - 23 (1 bit)
I/O analog switch register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
G0P0 : G0P0 analog switch enable
bits : 0 - 0 (1 bit)
G0P1 : G0P1 analog switch enable
bits : 1 - 1 (1 bit)
G0P2 : G0P2 analog switch enable
bits : 2 - 2 (1 bit)
G0P3 : G0P3 analog switch enable
bits : 3 - 3 (1 bit)
G1P0 : G1P0 analog switch enable
bits : 4 - 4 (1 bit)
G1P1 : G1P1 analog switch enable
bits : 5 - 5 (1 bit)
G1P2 : G1P2 analog switch enable
bits : 6 - 6 (1 bit)
G1P3 : G1P3 analog switch enable
bits : 7 - 7 (1 bit)
G2P0 : G2P0 analog switch enable
bits : 8 - 8 (1 bit)
G2P1 : G2P1 analog switch enable
bits : 9 - 9 (1 bit)
G2P2 : G2P2 analog switch enable
bits : 10 - 10 (1 bit)
G2P3 : G2P3 analog switch enable
bits : 11 - 11 (1 bit)
G3P0 : G3P0 analog switch enable
bits : 12 - 12 (1 bit)
G3P1 : G3P1 analog switch enable
bits : 13 - 13 (1 bit)
G3P2 : G3P2 analog switch enable
bits : 14 - 14 (1 bit)
G3P3 : G3P3 analog switch enable
bits : 15 - 15 (1 bit)
G4P0 : G4P0 analog switch enable
bits : 16 - 16 (1 bit)
G4P1 : G4P1 analog switch enable
bits : 17 - 17 (1 bit)
G4P2 : G4P2 analog switch enable
bits : 18 - 18 (1 bit)
G4P3 : G4P3 analog switch enable
bits : 19 - 19 (1 bit)
G5P0 : G5P0 analog switch enable
bits : 20 - 20 (1 bit)
G5P1 : G5P1 analog switch enable
bits : 21 - 21 (1 bit)
G5P2 : G5P2 analog switch enable
bits : 22 - 22 (1 bit)
G5P3 : G5P3 analog switch enable
bits : 23 - 23 (1 bit)
I/O sample configuration register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
G0P0 : G0P0 sampling mode
bits : 0 - 0 (1 bit)
G0P1 : G0P1 sampling mode
bits : 1 - 1 (1 bit)
G0P2 : G0P2 sampling mode
bits : 2 - 2 (1 bit)
G0P3 : G0P3 sampling mode
bits : 3 - 3 (1 bit)
G1P0 : G1P0 sampling mode
bits : 4 - 4 (1 bit)
G1P1 : G1P1 sampling mode
bits : 5 - 5 (1 bit)
G1P2 : G1P2 sampling mode
bits : 6 - 6 (1 bit)
G1P3 : G1P3 sampling mode
bits : 7 - 7 (1 bit)
G2P0 : G2P0 sampling mode
bits : 8 - 8 (1 bit)
G2P1 : G2P1 sampling mode
bits : 9 - 9 (1 bit)
G2P2 : G2P2 sampling mode
bits : 10 - 10 (1 bit)
G2P3 : G2P3 sampling mode
bits : 11 - 11 (1 bit)
G3P0 : G3P0 sampling mode
bits : 12 - 12 (1 bit)
G3P1 : G3P1 sampling mode
bits : 13 - 13 (1 bit)
G3P2 : G3P2 sampling mode
bits : 14 - 14 (1 bit)
G3P3 : G3P3 sampling mode
bits : 15 - 15 (1 bit)
G4P0 : G4P0 sampling mode
bits : 16 - 16 (1 bit)
G4P1 : G4P1 sampling mode
bits : 17 - 17 (1 bit)
G4P2 : G4P2 sampling mode
bits : 18 - 18 (1 bit)
G4P3 : G4P3 sampling mode
bits : 19 - 19 (1 bit)
G5P0 : G5P0 sampling mode
bits : 20 - 20 (1 bit)
G5P1 : G5P1 sampling mode
bits : 21 - 21 (1 bit)
G5P2 : G5P2 sampling mode
bits : 22 - 22 (1 bit)
G5P3 : G5P3 sampling mode
bits : 23 - 23 (1 bit)
I/O channel configuration register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
G0P0 : G0P0 channel mode
bits : 0 - 0 (1 bit)
G0P1 : G0P1 channel mode
bits : 1 - 1 (1 bit)
G0P2 : G0P2 channel mode
bits : 2 - 2 (1 bit)
G0P3 : G0P3 channel mode
bits : 3 - 3 (1 bit)
G1P0 : G1P0 channel mode
bits : 4 - 4 (1 bit)
G1P1 : G1P1 channel mode
bits : 5 - 5 (1 bit)
G1P2 : G1P2 channel mode
bits : 6 - 6 (1 bit)
G1P3 : G1P3 channel mode
bits : 7 - 7 (1 bit)
G2P0 : G2P0 channel mode
bits : 8 - 8 (1 bit)
G2P1 : G2P1 channel mode
bits : 9 - 9 (1 bit)
G2P2 : G2P2 channel mode
bits : 10 - 10 (1 bit)
G2P3 : G2P3 channel mode
bits : 11 - 11 (1 bit)
G3P0 : G3P0 channel mode
bits : 12 - 12 (1 bit)
G3P1 : G3P1 channel mode
bits : 13 - 13 (1 bit)
G3P2 : G3P2 channel mode
bits : 14 - 14 (1 bit)
G3P3 : G3P3 channel mode
bits : 15 - 15 (1 bit)
G4P0 : G4P0 channel mode
bits : 16 - 16 (1 bit)
G4P1 : G4P1 channel mode
bits : 17 - 17 (1 bit)
G4P2 : G4P2 channel mode
bits : 18 - 18 (1 bit)
G4P3 : G4P3 channel mode
bits : 19 - 19 (1 bit)
G5P0 : G5P0 channel mode
bits : 20 - 20 (1 bit)
G5P1 : G5P1 channel mode
bits : 21 - 21 (1 bit)
G5P2 : G5P2 channel mode
bits : 22 - 22 (1 bit)
G5P3 : G5P3 channel mode
bits : 23 - 23 (1 bit)
I/O group control register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GE0 : Analog I/O group x enable
bits : 0 - 0 (1 bit)
access : read-write
GE1 : Analog I/O group x enable
bits : 1 - 1 (1 bit)
access : read-write
GE2 : Analog I/O group x enable
bits : 2 - 2 (1 bit)
access : read-write
GE3 : Analog I/O group x enable
bits : 3 - 3 (1 bit)
access : read-write
GE4 : Analog I/O group x enable
bits : 4 - 4 (1 bit)
access : read-write
GE5 : Analog I/O group x enable
bits : 5 - 5 (1 bit)
access : read-write
GC0 : Analog I/O group x status
bits : 16 - 16 (1 bit)
access : read-only
GC1 : Analog I/O group x status
bits : 17 - 17 (1 bit)
access : read-only
GC2 : Analog I/O group x status
bits : 18 - 18 (1 bit)
access : read-only
GC3 : Analog I/O group x status
bits : 19 - 19 (1 bit)
access : read-only
GC4 : Analog I/O group x status
bits : 20 - 20 (1 bit)
access : read-only
GC5 : Analog I/O group x status
bits : 21 - 21 (1 bit)
access : read-only
control register 1
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTCDIV_MSB : Charge Transfer clock division factor
bits : 24 - 24 (1 bit)
ECDIV : Extend Charge clock division factor
bits : 28 - 29 (2 bit)
I/O group x cycle number register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CYCN : Cycle number
bits : 0 - 13 (14 bit)
I/O group x cycle number register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CYCN : Cycle number
bits : 0 - 13 (14 bit)
I/O group x cycle number register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CYCN : Cycle number
bits : 0 - 13 (14 bit)
interrupt enable register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTCFIE : Charge-transfer complete flag Interrupt Enable
bits : 0 - 0 (1 bit)
MNERRIE : Max Cycle Number Error Interrupt Enable
bits : 1 - 1 (1 bit)
I/O group x cycle number register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CYCN : Cycle number
bits : 0 - 13 (14 bit)
I/O group x cycle number register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CYCN : Cycle number
bits : 0 - 13 (14 bit)
I/O group x cycle number register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CYCN : Cycle number
bits : 0 - 13 (14 bit)
interrupt flag clear register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCTCF : Clear charge-transfer complete flag
bits : 0 - 0 (1 bit)
CMNERR : Clear max cycle number error
bits : 1 - 1 (1 bit)
interrupt flag register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTCF : End of acquisition flag
bits : 0 - 0 (1 bit)
MNERR : Max count error flag
bits : 1 - 1 (1 bit)
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