\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UEN : USART enable
bits : 0 - 0 (1 bit)
UESM : USART enable in Stop mode
bits : 1 - 1 (1 bit)
REN : Receiver enable
bits : 2 - 2 (1 bit)
TEN : Transmitter enable
bits : 3 - 3 (1 bit)
IDLEIE : IDLE interrupt enable
bits : 4 - 4 (1 bit)
RBNEIE : RXNE interrupt enable
bits : 5 - 5 (1 bit)
TCIE : Transmission complete interrupt enable
bits : 6 - 6 (1 bit)
TBEIE : interrupt enable
bits : 7 - 7 (1 bit)
PERRIE : PE interrupt enable
bits : 8 - 8 (1 bit)
PM : Parity selection
bits : 9 - 9 (1 bit)
PCEN : Parity control enable
bits : 10 - 10 (1 bit)
WM : Receiver wakeup method
bits : 11 - 11 (1 bit)
WL : Word length
bits : 12 - 12 (1 bit)
MEN : Mute mode enable
bits : 13 - 13 (1 bit)
AMIE : Character match interrupt enable
bits : 14 - 14 (1 bit)
OVSMOD : Oversampling mode
bits : 15 - 15 (1 bit)
DED : Driver Enable deassertion time
bits : 16 - 20 (5 bit)
DEA : Driver Enable assertion time
bits : 21 - 25 (5 bit)
RTIE : Receiver timeout interrupt enable
bits : 26 - 26 (1 bit)
EBIE : End of Block interrupt enable
bits : 27 - 27 (1 bit)
Guard time and prescaler register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : Prescaler value
bits : 0 - 7 (8 bit)
GUAT : Guard time value
bits : 8 - 15 (8 bit)
Receiver timeout register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RT : Receiver timeout value
bits : 0 - 23 (24 bit)
BL : Block Length
bits : 24 - 31 (8 bit)
Request register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ABDCMD : Auto baud rate request
bits : 0 - 0 (1 bit)
SBKCMD : Send break request
bits : 1 - 1 (1 bit)
MMCMD : Mute mode request
bits : 2 - 2 (1 bit)
RXFCMD : Receive data flush request
bits : 3 - 3 (1 bit)
TXFCMD : Transmit data flush request
bits : 4 - 4 (1 bit)
Interrupt and status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERR : Parity error
bits : 0 - 0 (1 bit)
FERR : Framing error
bits : 1 - 1 (1 bit)
NERR : Noise detected flag
bits : 2 - 2 (1 bit)
ORERR : Overrun error
bits : 3 - 3 (1 bit)
IDLEF : Idle line detected
bits : 4 - 4 (1 bit)
RBNE : Read data register not empty
bits : 5 - 5 (1 bit)
TC : Transmission complete
bits : 6 - 6 (1 bit)
TBE : Transmit data register empty
bits : 7 - 7 (1 bit)
LBDF : LIN break detection flag
bits : 8 - 8 (1 bit)
CTSF : CTS interrupt flag
bits : 9 - 9 (1 bit)
CTS : CTS flag
bits : 10 - 10 (1 bit)
RTF : Receiver timeout
bits : 11 - 11 (1 bit)
EBF : End of block flag
bits : 12 - 12 (1 bit)
ABDE : Auto baud rate error
bits : 14 - 14 (1 bit)
ABDF : Auto baud rate flag
bits : 15 - 15 (1 bit)
BSY : Busy flag
bits : 16 - 16 (1 bit)
AMF : character match flag
bits : 17 - 17 (1 bit)
SBF : Send break flag
bits : 18 - 18 (1 bit)
RWU : Receiver wakeup from Mute mode
bits : 19 - 19 (1 bit)
WUF : Wakeup from Stop mode flag
bits : 20 - 20 (1 bit)
TEA : Transmit enable acknowledge flag
bits : 21 - 21 (1 bit)
REA : Receive enable acknowledge flag
bits : 22 - 22 (1 bit)
Interrupt flag clear register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PEC : Parity error clear flag
bits : 0 - 0 (1 bit)
FEC : Framing error clear flag
bits : 1 - 1 (1 bit)
NEC : Noise detected clear flag
bits : 2 - 2 (1 bit)
OREC : Overrun error clear flag
bits : 3 - 3 (1 bit)
IDLEC : Idle line detected clear flag
bits : 4 - 4 (1 bit)
TCC : Transmission complete clear flag
bits : 6 - 6 (1 bit)
LBDC : LIN break detection clear flag
bits : 8 - 8 (1 bit)
CTSC : CTS clear flag
bits : 9 - 9 (1 bit)
RTC : Receiver timeout clear flag
bits : 11 - 11 (1 bit)
EBC : End of timeout clear flag
bits : 12 - 12 (1 bit)
AMC : Character match clear flag
bits : 17 - 17 (1 bit)
WUC : Wakeup from Stop mode clear flag
bits : 20 - 20 (1 bit)
Receive data register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATA : Receive data value
bits : 0 - 8 (9 bit)
Transmit data register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit data value
bits : 0 - 8 (9 bit)
Control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDM : 7-bit Address Detection/4-bit Address Detection
bits : 4 - 4 (1 bit)
LBLEN : LIN break detection length
bits : 5 - 5 (1 bit)
LBDIE : LIN break detection interrupt enable
bits : 6 - 6 (1 bit)
CLEN : Last bit clock pulse
bits : 8 - 8 (1 bit)
CPH : Clock phase
bits : 9 - 9 (1 bit)
CPL : Clock polarity
bits : 10 - 10 (1 bit)
CKEN : Clock enable
bits : 11 - 11 (1 bit)
STB : STOP bits
bits : 12 - 13 (2 bit)
LMEN : LIN mode enable
bits : 14 - 14 (1 bit)
STRP : Swap TX/RX pins
bits : 15 - 15 (1 bit)
RINV : RX pin active level inversion
bits : 16 - 16 (1 bit)
TINV : TX pin active level inversion
bits : 17 - 17 (1 bit)
DINV : Binary data inversion
bits : 18 - 18 (1 bit)
MSBF : Most significant bit first
bits : 19 - 19 (1 bit)
ABDEN : Auto baud rate enable
bits : 20 - 20 (1 bit)
ABDM : Auto baud rate mode
bits : 21 - 22 (2 bit)
RTEN : Receiver timeout enable
bits : 23 - 23 (1 bit)
ADDR : Address of the USART node
bits : 24 - 31 (8 bit)
Control register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERRIE : Error interrupt enable
bits : 0 - 0 (1 bit)
IREN : IrDA mode enable
bits : 1 - 1 (1 bit)
IRLP : IrDA low-power
bits : 2 - 2 (1 bit)
HDEN : Half-duplex selection
bits : 3 - 3 (1 bit)
NKEN : Smartcard NACK enable
bits : 4 - 4 (1 bit)
SCEN : Smartcard mode enable
bits : 5 - 5 (1 bit)
DENR : DMA enable receiver
bits : 6 - 6 (1 bit)
DENT : DMA enable transmitter
bits : 7 - 7 (1 bit)
RTSEN : RTS enable
bits : 8 - 8 (1 bit)
CTSEN : CTS enable
bits : 9 - 9 (1 bit)
CTSIE : CTS interrupt enable
bits : 10 - 10 (1 bit)
OSB : One sample bit method enable
bits : 11 - 11 (1 bit)
OVRD : Overrun Disable
bits : 12 - 12 (1 bit)
DDRE : DMA Disable on Reception Error
bits : 13 - 13 (1 bit)
DEM : Driver enable mode
bits : 14 - 14 (1 bit)
DEP : Driver enable polarity selection
bits : 15 - 15 (1 bit)
SCRTNUM : Smartcard auto-retry count
bits : 17 - 19 (3 bit)
WUM : Wakeup from Stop mode interrupt flag selection
bits : 20 - 21 (2 bit)
WUIE : Wakeup from Stop mode interrupt enable
bits : 22 - 22 (1 bit)
Baud rate register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRR_FRA : integer of baud-rate divider
bits : 0 - 3 (4 bit)
BRR_INT : integer of baud-rate divider
bits : 4 - 15 (12 bit)
USART receive FIFO control and status register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ELNACK : Early NKEN when smartcard mode is selected
bits : 0 - 0 (1 bit)
RFEN : Receive FIFO enable
bits : 8 - 8 (1 bit)
RFFIE : Receive FIFO full interrupt enable
bits : 9 - 9 (1 bit)
RFE : Receive FIFO empty flag
bits : 10 - 10 (1 bit)
RFF : Receive FIFO full flag
bits : 11 - 11 (1 bit)
RFCNT : Receive FIFO count number
bits : 12 - 14 (3 bit)
RFFINT : Receive FIFO full interrupt flag
bits : 15 - 15 (1 bit)
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