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USBFS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

HCTL

HPTFQSTAT

HCH0CTL

HCH0INTF

HCH0INTEN

HCH0LEN

HCH1CTL

HCH1INTF

HCH1INTEN

HCH1LEN

HACHINT

HCH2CTL

HCH2INTF

HCH2INTEN

HCH2LEN

HCH3CTL

HCH3INTF

HCH3INTEN

HCH3LEN

HACHINTEN

HCH4CTL

HCH4INTF

HCH4INTEN

HCH4LEN

HCH5CTL

HCH5INTF

HCH5INTEN

HCH5LEN

HCH6CTL

HCH6INTF

HCH6INTEN

HCH6LEN

HCH7CTL

HCH7INTF

HCH7INTEN

HCH7LEN

HFT

HPCS

HFINFR


HCTL

host configuration register (HCTL)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCTL HCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKSEL

CLKSEL : clock select for USB clock
bits : 0 - 1 (2 bit)
access : read-write


HPTFQSTAT

Host periodic transmit FIFO/queue status register (HPTFQSTAT)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HPTFQSTAT HPTFQSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTXFS PTXREQS PTXREQT

PTXFS : Periodic transmit data FIFO space available
bits : 0 - 15 (16 bit)
access : read-only

PTXREQS : Periodic transmit request queue space available
bits : 16 - 23 (8 bit)
access : read-only

PTXREQT : Top of the periodic transmit request queue
bits : 24 - 31 (8 bit)
access : read-only


HCH0CTL

host channel-0 characteristics register (HCH0CTL)
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH0CTL HCH0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPL EPNUM EPDIR LSD EPTYPE DAR ODDFRM CDIS CEN

MPL : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSD : Low-speed device
bits : 17 - 17 (1 bit)

EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)

DAR : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CDIS : Channel disable
bits : 30 - 30 (1 bit)

CEN : Channel enable
bits : 31 - 31 (1 bit)


HCH0INTF

host channel-0 interrupt register (USBFS_HCHxINTF)
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH0INTF HCH0INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF CH STALL NAK ACK USBER BBER REQOVR DTER

TF : Transfer finished
bits : 0 - 0 (1 bit)

CH : Channel halted
bits : 1 - 1 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

USBER : USB bus error
bits : 7 - 7 (1 bit)

BBER : Babble error
bits : 8 - 8 (1 bit)

REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)

DTER : Data toggle error
bits : 10 - 10 (1 bit)


HCH0INTEN

host channel-0 interrupt enable register (HCH0INTEN)
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH0INTEN HCH0INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIE CHIE STALLIE NAKIE ACKIE USBERIE BBERIE REQOVRIE DTERIE

TFIE : Transfer completed interrupt enable
bits : 0 - 0 (1 bit)

CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)

STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)

NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)

ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)

USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)

BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)

REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)

DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)


HCH0LEN

host channel-0 transfer length register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH0LEN HCH0LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEN PCNT DPID

TLEN : Transfer length
bits : 0 - 18 (19 bit)

PCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


HCH1CTL

host channel-1 characteristics register (HCH1CTL)
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH1CTL HCH1CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPL EPNUM EPDIR LSD EPTYPE DAR ODDFRM CDIS CEN

MPL : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSD : Low-speed device
bits : 17 - 17 (1 bit)

EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)

DAR : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CDIS : Channel disable
bits : 30 - 30 (1 bit)

CEN : Channel enable
bits : 31 - 31 (1 bit)


HCH1INTF

host channel-1 interrupt register (HCH1INTF)
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH1INTF HCH1INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF CH STALL NAK ACK USBER BBER REQOVR DTER

TF : Transfer finished
bits : 0 - 0 (1 bit)

CH : Channel halted
bits : 1 - 1 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

USBER : USB bus error
bits : 7 - 7 (1 bit)

BBER : Babble error
bits : 8 - 8 (1 bit)

REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)

DTER : Data toggle error
bits : 10 - 10 (1 bit)


HCH1INTEN

host channel-1 interrupt enable register (HCH1INTEN)
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH1INTEN HCH1INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIE CHIE STALLIE NAKIE ACKIE USBERIE BBERIE REQOVRIE DTERIE

TFIE : Transfer completed interrupt enable
bits : 0 - 0 (1 bit)

CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)

STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)

NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)

ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)

USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)

BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)

REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)

DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)


HCH1LEN

host channel-1 transfer length register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH1LEN HCH1LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEN PCNT DPID

TLEN : Transfer length
bits : 0 - 18 (19 bit)

PCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


HACHINT

Host all channels interrupt register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HACHINT HACHINT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HACHINT

HACHINT : Host all channel interrupts
bits : 0 - 7 (8 bit)


HCH2CTL

host channel-2 characteristics register (HCH2CTL)
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH2CTL HCH2CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPL EPNUM EPDIR LSD EPTYPE DAR ODDFRM CDIS CEN

MPL : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSD : Low-speed device
bits : 17 - 17 (1 bit)

EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)

DAR : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CDIS : Channel disable
bits : 30 - 30 (1 bit)

CEN : Channel enable
bits : 31 - 31 (1 bit)


HCH2INTF

host channel-2 interrupt register (HCH2INTF)
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH2INTF HCH2INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF CH STALL NAK ACK USBER BBER REQOVR DTER

TF : Transfer finished
bits : 0 - 0 (1 bit)

CH : Channel halted
bits : 1 - 1 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

USBER : USB bus error
bits : 7 - 7 (1 bit)

BBER : Babble error
bits : 8 - 8 (1 bit)

REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)

DTER : Data toggle error
bits : 10 - 10 (1 bit)


HCH2INTEN

host channel-2 interrupt enable register (HCH2INTEN)
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH2INTEN HCH2INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIE CHIE STALLIE NAKIE ACKIE USBERIE BBERIE REQOVRIE DTERIE

TFIE : Transfer completed interrupt enable
bits : 0 - 0 (1 bit)

CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)

STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)

NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)

ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)

USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)

BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)

REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)

DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)


HCH2LEN

host channel-2 transfer length register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH2LEN HCH2LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEN PCNT DPID

TLEN : Transfer length
bits : 0 - 18 (19 bit)

PCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


HCH3CTL

host channel-3 characteristics register (HCH3CTL)
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH3CTL HCH3CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPL EPNUM EPDIR LSD EPTYPE DAR ODDFRM CDIS CEN

MPL : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSD : Low-speed device
bits : 17 - 17 (1 bit)

EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)

DAR : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CDIS : Channel disable
bits : 30 - 30 (1 bit)

CEN : Channel enable
bits : 31 - 31 (1 bit)


HCH3INTF

host channel-3 interrupt register (HCH3INTF)
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH3INTF HCH3INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF CH STALL NAK ACK USBER BBER REQOVR DTER

TF : Transfer finished
bits : 0 - 0 (1 bit)

CH : Channel halted
bits : 1 - 1 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

USBER : USB bus error
bits : 7 - 7 (1 bit)

BBER : Babble error
bits : 8 - 8 (1 bit)

REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)

DTER : Data toggle error
bits : 10 - 10 (1 bit)


HCH3INTEN

host channel-3 interrupt enable register (HCH3INTEN)
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH3INTEN HCH3INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIE CHIE STALLIE NAKIE ACKIE USBERIE BBERIE REQOVRIE DTERIE

TFIE : Transfer completed interrupt enable
bits : 0 - 0 (1 bit)

CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)

STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)

NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)

ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)

USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)

BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)

REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)

DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)


HCH3LEN

host channel-3 transfer length register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH3LEN HCH3LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEN PCNT DPID

TLEN : Transfer length
bits : 0 - 18 (19 bit)

PCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


HACHINTEN

host all channels interrupt mask register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HACHINTEN HACHINTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CINTEN

CINTEN : Channel interrupt enable
bits : 0 - 7 (8 bit)


HCH4CTL

host channel-4 characteristics register (HCH4CTL)
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH4CTL HCH4CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPL EPNUM EPDIR LSD EPTYPE DAR ODDFRM CDIS CEN

MPL : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSD : Low-speed device
bits : 17 - 17 (1 bit)

EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)

DAR : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CDIS : Channel disable
bits : 30 - 30 (1 bit)

CEN : Channel enable
bits : 31 - 31 (1 bit)


HCH4INTF

host channel-4 interrupt register (HCH4INTF)
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH4INTF HCH4INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF CH STALL NAK ACK USBER BBER REQOVR DTER

TF : Transfer finished
bits : 0 - 0 (1 bit)

CH : Channel halted
bits : 1 - 1 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

USBER : USB bus error
bits : 7 - 7 (1 bit)

BBER : Babble error
bits : 8 - 8 (1 bit)

REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)

DTER : Data toggle error
bits : 10 - 10 (1 bit)


HCH4INTEN

host channel-4 interrupt enable register (HCH4INTEN)
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH4INTEN HCH4INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIE CHIE STALLIE NAKIE ACKIE USBERIE BBERIE REQOVRIE DTERIE

TFIE : Transfer completed interrupt enable
bits : 0 - 0 (1 bit)

CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)

STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)

NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)

ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)

USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)

BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)

REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)

DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)


HCH4LEN

host channel-4 transfer length register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH4LEN HCH4LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEN PCNT DPID

TLEN : Transfer length
bits : 0 - 18 (19 bit)

PCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


HCH5CTL

host channel-5 characteristics register (HCH5CTL)
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH5CTL HCH5CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPL EPNUM EPDIR LSD EPTYPE DAR ODDFRM CDIS CEN

MPL : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSD : Low-speed device
bits : 17 - 17 (1 bit)

EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)

DAR : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CDIS : Channel disable
bits : 30 - 30 (1 bit)

CEN : Channel enable
bits : 31 - 31 (1 bit)


HCH5INTF

host channel-5 interrupt register (HCH5INTF)
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH5INTF HCH5INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF CH STALL NAK ACK USBER BBER REQOVR DTER

TF : Transfer finished
bits : 0 - 0 (1 bit)

CH : Channel halted
bits : 1 - 1 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

USBER : USB bus error
bits : 7 - 7 (1 bit)

BBER : Babble error
bits : 8 - 8 (1 bit)

REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)

DTER : Data toggle error
bits : 10 - 10 (1 bit)


HCH5INTEN

host channel-5 interrupt enable register (HCH5INTEN)
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH5INTEN HCH5INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIE CHIE STALLIE NAKIE ACKIE USBERIE BBERIE REQOVRIE DTERIE

TFIE : Transfer completed interrupt enable
bits : 0 - 0 (1 bit)

CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)

STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)

NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)

ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)

USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)

BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)

REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)

DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)


HCH5LEN

host channel-5 transfer length register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH5LEN HCH5LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEN PCNT DPID

TLEN : Transfer length
bits : 0 - 18 (19 bit)

PCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


HCH6CTL

host channel-6 characteristics register (HCH6CTL)
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH6CTL HCH6CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPL EPNUM EPDIR LSD EPTYPE DAR ODDFRM CDIS CEN

MPL : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSD : Low-speed device
bits : 17 - 17 (1 bit)

EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)

DAR : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CDIS : Channel disable
bits : 30 - 30 (1 bit)

CEN : Channel enable
bits : 31 - 31 (1 bit)


HCH6INTF

host channel-6 interrupt register (HCH6INTF)
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH6INTF HCH6INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF CH STALL NAK ACK USBER BBER REQOVR DTER

TF : Transfer finished
bits : 0 - 0 (1 bit)

CH : Channel halted
bits : 1 - 1 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

USBER : USB bus error
bits : 7 - 7 (1 bit)

BBER : Babble error
bits : 8 - 8 (1 bit)

REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)

DTER : Data toggle error
bits : 10 - 10 (1 bit)


HCH6INTEN

host channel-6 interrupt enable register (HCH6INTEN)
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH6INTEN HCH6INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIE CHIE STALLIE NAKIE ACKIE USBERIE BBERIE REQOVRIE DTERIE

TFIE : Transfer completed interrupt enable
bits : 0 - 0 (1 bit)

CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)

STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)

NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)

ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)

USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)

BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)

REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)

DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)


HCH6LEN

host channel-6 transfer length register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH6LEN HCH6LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEN PCNT DPID

TLEN : Transfer length
bits : 0 - 18 (19 bit)

PCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


HCH7CTL

host channel-7 characteristics register (HCH7CTL)
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH7CTL HCH7CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPL EPNUM EPDIR LSD EPTYPE DAR ODDFRM CDIS CEN

MPL : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSD : Low-speed device
bits : 17 - 17 (1 bit)

EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)

DAR : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CDIS : Channel disable
bits : 30 - 30 (1 bit)

CEN : Channel enable
bits : 31 - 31 (1 bit)


HCH7INTF

host channel-7 interrupt register (HCH7INTF)
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH7INTF HCH7INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF CH STALL NAK ACK USBER BBER REQOVR DTER

TF : Transfer finished
bits : 0 - 0 (1 bit)

CH : Channel halted
bits : 1 - 1 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

USBER : USB bus error
bits : 7 - 7 (1 bit)

BBER : Babble error
bits : 8 - 8 (1 bit)

REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)

DTER : Data toggle error
bits : 10 - 10 (1 bit)


HCH7INTEN

host channel-7 interrupt enable register (HCH7INTEN)
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH7INTEN HCH7INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIE CHIE STALLIE NAKIE ACKIE USBERIE BBERIE REQOVRIE DTERIE

TFIE : Transfer completed interrupt enable
bits : 0 - 0 (1 bit)

CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)

STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)

NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)

ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)

USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)

BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)

REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)

DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)


HCH7LEN

host channel-7 transfer length register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH7LEN HCH7LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEN PCNT DPID

TLEN : Transfer length
bits : 0 - 18 (19 bit)

PCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


HFT

Host frame interval register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFT HFT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRI

FRI : Frame interval
bits : 0 - 15 (16 bit)


HPCS

Host port control and status register (USBFS_HPCS)
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HPCS HPCS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCST PCD PE PEDC PREM PSP PRST PLST PP PS

PCST : Port connect status
bits : 0 - 0 (1 bit)
access : read-only

PCD : Port connect detected
bits : 1 - 1 (1 bit)
access : read-write

PE : Port enable
bits : 2 - 2 (1 bit)
access : read-write

PEDC : Port enable/disable change
bits : 3 - 3 (1 bit)
access : read-write

PREM : Port resume
bits : 6 - 6 (1 bit)
access : read-write

PSP : Port suspend
bits : 7 - 7 (1 bit)
access : read-write

PRST : Port reset
bits : 8 - 8 (1 bit)
access : read-write

PLST : Port line status
bits : 10 - 11 (2 bit)
access : read-only

PP : Port power
bits : 12 - 12 (1 bit)
access : read-write

PS : Port speed
bits : 17 - 18 (2 bit)
access : read-only


HFINFR

OTG_FS host frame number/frame time remaining register (HFINFR)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HFINFR HFINFR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRNUM FRT

FRNUM : Frame number
bits : 0 - 15 (16 bit)

FRT : Frame remaining time
bits : 16 - 31 (16 bit)



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