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EXMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

SNCTL0

SNCTL2

SNWTCFG0

SNWTCFG1

SNWTCFG2

SNWTCFG3

SNTCFG2

SNCTL3

SNTCFG3

SNTCFG0

NPCTL1

NPINTEN1

NPCTCFG1

NPATCFG1

NECC1

SNCTL1

NPCTL2

NPINTEN2

NPCTCFG2

NPATCFG2

NECC2

NPCTL3

NPINTEN3

NPCTCFG3

NPATCFG3

PIOTCFG3

SNTCFG1


SNCTL0

SRAM/NOR flash control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNCTL0 SNCTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NRBKEN NRMUX NRTP NRW NREN SBRSTEN NRWTPOL WRAPEN NRWTCFG WREN NRWTEN EXMODEN ASYNCWAIT CPS SYNCWR

NRBKEN : NOR bank enable
bits : 0 - 0 (1 bit)

NRMUX : NOR bank memory address/data multiplexing
bits : 1 - 1 (1 bit)

NRTP : NOR bank memory type
bits : 2 - 3 (2 bit)

NRW : NOR bank memory data bus width
bits : 4 - 5 (2 bit)

NREN : NOR Flash access enable
bits : 6 - 6 (1 bit)

SBRSTEN : Synchronous burst enable
bits : 8 - 8 (1 bit)

NRWTPOL : NWAIT signal polarity
bits : 9 - 9 (1 bit)

WRAPEN : Wrapped burst mode enable
bits : 10 - 10 (1 bit)

NRWTCFG : NWAIT signal configuration, only work in synchronous mode
bits : 11 - 11 (1 bit)

WREN : Write enable
bits : 12 - 12 (1 bit)

NRWTEN : NWAIT signal enable
bits : 13 - 13 (1 bit)

EXMODEN : Extended mode enable
bits : 14 - 14 (1 bit)

ASYNCWAIT : Asynchronous wait
bits : 15 - 15 (1 bit)

CPS : CRAM page size
bits : 16 - 18 (3 bit)

SYNCWR : Synchronous write
bits : 19 - 19 (1 bit)


SNCTL2

SRAM/NOR flash control register 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNCTL2 SNCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NRBKEN NRMUX NRTP NRW NREN SBRSTEN NRWTPOL WRAPEN NRWTCFG WREN NRWTEN EXMODEN ASYNCWAIT CPS SYNCWR

NRBKEN : NOR bank enable
bits : 0 - 0 (1 bit)

NRMUX : NOR bank memory address/data multiplexing
bits : 1 - 1 (1 bit)

NRTP : NOR bank memory type
bits : 2 - 3 (2 bit)

NRW : NOR bank memory data bus width
bits : 4 - 5 (2 bit)

NREN : NOR Flash access enable
bits : 6 - 6 (1 bit)

SBRSTEN : Synchronous burst enable
bits : 8 - 8 (1 bit)

NRWTPOL : NWAIT signal polarity
bits : 9 - 9 (1 bit)

WRAPEN : Wrapped burst mode enable
bits : 10 - 10 (1 bit)

NRWTCFG : NWAIT signal configuration, only work in synchronous mode
bits : 11 - 11 (1 bit)

WREN : Write enable
bits : 12 - 12 (1 bit)

NRWTEN : NWAIT signal enable
bits : 13 - 13 (1 bit)

EXMODEN : Extended mode enable
bits : 14 - 14 (1 bit)

ASYNCWAIT : Asynchronous wait
bits : 15 - 15 (1 bit)

CPS : CRAM page size
bits : 16 - 18 (3 bit)

SYNCWR : Synchronous write
bits : 19 - 19 (1 bit)


SNWTCFG0

SRAM/NOR flash write timing configuration register 0
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNWTCFG0 SNWTCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WASET WAHLD WDSET WBUSLAT WASYNCMOD

WASET : Address setup time
bits : 0 - 3 (4 bit)

WAHLD : Address hold time
bits : 4 - 7 (4 bit)

WDSET : Data setup time
bits : 8 - 15 (8 bit)

WBUSLAT : Bus latency
bits : 16 - 19 (4 bit)

WASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)


SNWTCFG1

SRAM/NOR flash write timing configuration register 1
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNWTCFG1 SNWTCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WASET WAHLD WDSET WBUSLAT WASYNCMOD

WASET : Address setup time
bits : 0 - 3 (4 bit)

WAHLD : Address hold time
bits : 4 - 7 (4 bit)

WDSET : Data setup time
bits : 8 - 15 (8 bit)

WBUSLAT : Bus latency
bits : 16 - 19 (4 bit)

WASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)


SNWTCFG2

SRAM/NOR flash write timing configuration register 2
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNWTCFG2 SNWTCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WASET WAHLD WDSET WBUSLAT WASYNCMOD

WASET : Address setup time
bits : 0 - 3 (4 bit)

WAHLD : Address hold time
bits : 4 - 7 (4 bit)

WDSET : Data setup time
bits : 8 - 15 (8 bit)

WBUSLAT : Bus latency
bits : 16 - 19 (4 bit)

WASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)


SNWTCFG3

SRAM/NOR flash write timing configuration register 3
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNWTCFG3 SNWTCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WASET WAHLD WDSET WBUSLAT WASYNCMOD

WASET : Address setup time
bits : 0 - 3 (4 bit)

WAHLD : Address hold time
bits : 4 - 7 (4 bit)

WDSET : Data setup time
bits : 8 - 15 (8 bit)

WBUSLAT : Bus latency
bits : 16 - 19 (4 bit)

WASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)


SNTCFG2

SRAM/NOR flash timing configuration register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNTCFG2 SNTCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASET AHLD DSET BUSLAT CKDIV DLAT ASYNCMOD

ASET : Address setup time
bits : 0 - 3 (4 bit)

AHLD : Address hold time
bits : 4 - 7 (4 bit)

DSET : Data setup time
bits : 8 - 15 (8 bit)

BUSLAT : Bus latency
bits : 16 - 19 (4 bit)

CKDIV : Synchronous clock divide ratio
bits : 20 - 23 (4 bit)

DLAT : Data latency for NOR Flash
bits : 24 - 27 (4 bit)

ASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)


SNCTL3

SRAM/NOR flash control register 3
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNCTL3 SNCTL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NRBKEN NRMUX NRTP NRW NREN SBRSTEN NRWTPOL WRAPEN NRWTCFG WREN NRWTEN EXMODEN ASYNCWAIT CPS SYNCWR

NRBKEN : NOR bank enable
bits : 0 - 0 (1 bit)

NRMUX : NOR bank memory address/data multiplexing
bits : 1 - 1 (1 bit)

NRTP : NOR bank memory type
bits : 2 - 3 (2 bit)

NRW : NOR bank memory data bus width
bits : 4 - 5 (2 bit)

NREN : NOR Flash access enable
bits : 6 - 6 (1 bit)

SBRSTEN : Synchronous burst enable
bits : 8 - 8 (1 bit)

NRWTPOL : NWAIT signal polarity
bits : 9 - 9 (1 bit)

WRAPEN : Wrapped burst mode enable
bits : 10 - 10 (1 bit)

NRWTCFG : NWAIT signal configuration, only work in synchronous mode
bits : 11 - 11 (1 bit)

WREN : Write enable
bits : 12 - 12 (1 bit)

NRWTEN : NWAIT signal enable
bits : 13 - 13 (1 bit)

EXMODEN : Extended mode enable
bits : 14 - 14 (1 bit)

ASYNCWAIT : Asynchronous wait
bits : 15 - 15 (1 bit)

CPS : CRAM page size
bits : 16 - 18 (3 bit)

SYNCWR : Synchronous write
bits : 19 - 19 (1 bit)


SNTCFG3

SRAM/NOR flash timing configuration register 3
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNTCFG3 SNTCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASET AHLD DSET BUSLAT CKDIV DLAT ASYNCMOD

ASET : Address setup time
bits : 0 - 3 (4 bit)

AHLD : Address hold time
bits : 4 - 7 (4 bit)

DSET : Data setup time
bits : 8 - 15 (8 bit)

BUSLAT : Bus latency
bits : 16 - 19 (4 bit)

CKDIV : Synchronous clock divide ratio
bits : 20 - 23 (4 bit)

DLAT : Data latency for NOR Flash
bits : 24 - 27 (4 bit)

ASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)


SNTCFG0

SRAM/NOR flash timing configuration register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNTCFG0 SNTCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASET AHLD DSET BUSLAT CKDIV DLAT ASYNCMOD

ASET : Address setup time
bits : 0 - 3 (4 bit)

AHLD : Address hold time
bits : 4 - 7 (4 bit)

DSET : Data setup time
bits : 8 - 15 (8 bit)

BUSLAT : Bus latency
bits : 16 - 19 (4 bit)

CKDIV : Synchronous clock divide ratio
bits : 20 - 23 (4 bit)

DLAT : Data latency for NOR Flash
bits : 24 - 27 (4 bit)

ASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)


NPCTL1

NAND flash/PC card control register 1
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPCTL1 NPCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDWTEN NDBKEN NDTP NDW ECCEN CTR ATR ECCSZ

NDWTEN : Wait feature enable
bits : 1 - 1 (1 bit)

NDBKEN : NAND bank enable
bits : 2 - 2 (1 bit)

NDTP : NAND bank memory type
bits : 3 - 3 (1 bit)

NDW : NAND bank memory data bus width
bits : 4 - 5 (2 bit)

ECCEN : ECC enable
bits : 6 - 6 (1 bit)

CTR : CLE to RE delay
bits : 9 - 12 (4 bit)

ATR : ALE to RE delay
bits : 13 - 16 (4 bit)

ECCSZ : ECC size
bits : 17 - 19 (3 bit)


NPINTEN1

NAND flash/PC card interrupt enable register 1
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPINTEN1 NPINTEN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTRS INTHS INTFS INTREN INTHEN INTFEN FFEPT

INTRS : Interrupt rising edge status
bits : 0 - 0 (1 bit)

INTHS : Interrupt high-level status
bits : 1 - 1 (1 bit)

INTFS : Interrupt falling edge status
bits : 2 - 2 (1 bit)

INTREN : Interrupt rising edge detection enable bit
bits : 3 - 3 (1 bit)

INTHEN : Interrupt high-level detection enable
bits : 4 - 4 (1 bit)

INTFEN : Interrupt falling edge detection enable
bits : 5 - 5 (1 bit)

FFEPT : FIFO empty flag
bits : 6 - 6 (1 bit)


NPCTCFG1

NAND flash/PC card common space timing configuration register 1
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPCTCFG1 NPCTCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMSET COMWAIT COMHLD COMHIZ

COMSET : Common memory setup time
bits : 0 - 7 (8 bit)

COMWAIT : Common memory wait time
bits : 8 - 15 (8 bit)

COMHLD : Common memory hold time
bits : 16 - 23 (8 bit)

COMHIZ : Common memory data bus HiZ time
bits : 24 - 31 (8 bit)


NPATCFG1

NAND flash/PC card attribute space timing configuration register 1
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPATCFG1 NPATCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATTSET ATTWAIT ATTHLD ATTHIZ

ATTSET : Attribute memory setup time
bits : 0 - 7 (8 bit)

ATTWAIT : Attribute memory wait time
bits : 8 - 15 (8 bit)

ATTHLD : Attribute memory hold time
bits : 16 - 23 (8 bit)

ATTHIZ : Attribute memory data bus HiZ time
bits : 24 - 31 (8 bit)


NECC1

NAND flash ECC register 1
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NECC1 NECC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECC

ECC : ECC result
bits : 0 - 31 (32 bit)
access : read-only


SNCTL1

SRAM/NOR flash control register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNCTL1 SNCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NRBKEN NRMUX NRTP NRW NREN SBRSTEN NRWTPOL WRAPEN NRWTCFG WREN NRWTEN EXMODEN ASYNCWAIT CPS SYNCWR

NRBKEN : NOR bank enable
bits : 0 - 0 (1 bit)

NRMUX : NOR bank memory address/data multiplexing
bits : 1 - 1 (1 bit)

NRTP : NOR bank memory type
bits : 2 - 3 (2 bit)

NRW : NOR bank memory data bus width
bits : 4 - 5 (2 bit)

NREN : NOR Flash access enable
bits : 6 - 6 (1 bit)

SBRSTEN : Synchronous burst enable
bits : 8 - 8 (1 bit)

NRWTPOL : NWAIT signal polarity
bits : 9 - 9 (1 bit)

WRAPEN : Wrapped burst mode enable
bits : 10 - 10 (1 bit)

NRWTCFG : NWAIT signal configuration, only work in synchronous mode
bits : 11 - 11 (1 bit)

WREN : Write enable
bits : 12 - 12 (1 bit)

NRWTEN : NWAIT signal enable
bits : 13 - 13 (1 bit)

EXMODEN : Extended mode enable
bits : 14 - 14 (1 bit)

ASYNCWAIT : Asynchronous wait
bits : 15 - 15 (1 bit)

CPS : CRAM page size
bits : 16 - 18 (3 bit)

SYNCWR : Synchronous write
bits : 19 - 19 (1 bit)


NPCTL2

NAND flash/PC card control register 2
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPCTL2 NPCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDWTEN NDBKEN NDTP NDW ECCEN CTR ATR ECCSZ

NDWTEN : Wait feature enable
bits : 1 - 1 (1 bit)

NDBKEN : NAND bank enable
bits : 2 - 2 (1 bit)

NDTP : NAND bank memory type
bits : 3 - 3 (1 bit)

NDW : NAND bank memory data bus width
bits : 4 - 5 (2 bit)

ECCEN : ECC enable
bits : 6 - 6 (1 bit)

CTR : CLE to RE delay
bits : 9 - 12 (4 bit)

ATR : ALE to RE delay
bits : 13 - 16 (4 bit)

ECCSZ : ECC size
bits : 17 - 19 (3 bit)


NPINTEN2

NAND flash/PC card interrupt enable register 2
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPINTEN2 NPINTEN2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTRS INTHS INTFS INTREN INTHEN INTFEN FFEPT

INTRS : Interrupt rising edge status
bits : 0 - 0 (1 bit)

INTHS : Interrupt high-level status
bits : 1 - 1 (1 bit)

INTFS : Interrupt falling edge status
bits : 2 - 2 (1 bit)

INTREN : Interrupt rising edge detection enable bit
bits : 3 - 3 (1 bit)

INTHEN : Interrupt high-level detection enable
bits : 4 - 4 (1 bit)

INTFEN : Interrupt falling edge detection enable
bits : 5 - 5 (1 bit)

FFEPT : FIFO empty flag
bits : 6 - 6 (1 bit)


NPCTCFG2

NAND flash/PC card common space timing configuration register 2
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPCTCFG2 NPCTCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMSET COMWAIT COMHLD COMHIZ

COMSET : Common memory setup time
bits : 0 - 7 (8 bit)

COMWAIT : Common memory wait time
bits : 8 - 15 (8 bit)

COMHLD : Common memory hold time
bits : 16 - 23 (8 bit)

COMHIZ : Common memory data bus HiZ time
bits : 24 - 31 (8 bit)


NPATCFG2

NAND flash/PC card attribute space timing configuration register 2
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPATCFG2 NPATCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATTSET ATTWAIT ATTHLD ATTHIZ

ATTSET : Attribute memory setup time
bits : 0 - 7 (8 bit)

ATTWAIT : Attribute memory wait time
bits : 8 - 15 (8 bit)

ATTHLD : Attribute memory hold time
bits : 16 - 23 (8 bit)

ATTHIZ : Attribute memory data bus HiZ time
bits : 24 - 31 (8 bit)


NECC2

NAND flash ECC register 2
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NECC2 NECC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECC

ECC : ECC result
bits : 0 - 31 (32 bit)
access : read-only


NPCTL3

NAND flash/PC card control register 3
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPCTL3 NPCTL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDWTEN NDBKEN NDTP NDW ECCEN CTR ATR ECCSZ

NDWTEN : Wait feature enable
bits : 1 - 1 (1 bit)

NDBKEN : NAND bank enable
bits : 2 - 2 (1 bit)

NDTP : NAND bank memory type
bits : 3 - 3 (1 bit)

NDW : NAND bank memory data bus width
bits : 4 - 5 (2 bit)

ECCEN : ECC enable
bits : 6 - 6 (1 bit)

CTR : CLE to RE delay
bits : 9 - 12 (4 bit)

ATR : ALE to RE delay
bits : 13 - 16 (4 bit)

ECCSZ : ECC size
bits : 17 - 19 (3 bit)


NPINTEN3

NAND flash/PC card interrupt enable register 3
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPINTEN3 NPINTEN3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTRS INTHS INTFS INTREN INTHEN INTFEN FFEPT

INTRS : Interrupt rising edge status
bits : 0 - 0 (1 bit)

INTHS : Interrupt high-level status
bits : 1 - 1 (1 bit)

INTFS : Interrupt falling edge status
bits : 2 - 2 (1 bit)

INTREN : Interrupt rising edge detection enable bit
bits : 3 - 3 (1 bit)

INTHEN : Interrupt high-level detection enable
bits : 4 - 4 (1 bit)

INTFEN : Interrupt falling edge detection enable
bits : 5 - 5 (1 bit)

FFEPT : FIFO empty flag
bits : 6 - 6 (1 bit)


NPCTCFG3

NAND flash/PC card common space timing configuration register 3
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPCTCFG3 NPCTCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMSET COMWAIT COMHLD COMHIZ

COMSET : Common memory setup time
bits : 0 - 7 (8 bit)

COMWAIT : Common memory wait time
bits : 8 - 15 (8 bit)

COMHLD : Common memory hold time
bits : 16 - 23 (8 bit)

COMHIZ : Common memory data bus HiZ time
bits : 24 - 31 (8 bit)


NPATCFG3

NAND flash/PC card attribute space timing configuration register 3
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPATCFG3 NPATCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATTSET ATTWAIT ATTHLD ATTHIZ

ATTSET : Attribute memory setup time
bits : 0 - 7 (8 bit)

ATTWAIT : Attribute memory wait time
bits : 8 - 15 (8 bit)

ATTHLD : Attribute memory hold time
bits : 16 - 23 (8 bit)

ATTHIZ : Attribute memory data bus HiZ time
bits : 24 - 31 (8 bit)


PIOTCFG3

PC card I/O space timing configuration register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIOTCFG3 PIOTCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSET IOWAIT IOHLD IOHIZ

IOSET : IO space setup time
bits : 0 - 7 (8 bit)

IOWAIT : IO space wait time
bits : 8 - 15 (8 bit)

IOHLD : IO space hold time
bits : 16 - 23 (8 bit)

IOHIZ : IO space data bus HiZ time
bits : 24 - 31 (8 bit)


SNTCFG1

SRAM/NOR flash timing configuration register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNTCFG1 SNTCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASET AHLD DSET BUSLAT CKDIV DLAT ASYNCMOD

ASET : Address setup time
bits : 0 - 3 (4 bit)

AHLD : Address hold time
bits : 4 - 7 (4 bit)

DSET : Data setup time
bits : 8 - 15 (8 bit)

BUSLAT : Bus latency
bits : 16 - 19 (4 bit)

CKDIV : Synchronous clock divide ratio
bits : 20 - 23 (4 bit)

DLAT : Data latency for NOR Flash
bits : 24 - 27 (4 bit)

ASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)



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