\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
power control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDOLP : LDO Low Power Mode
bits : 0 - 0 (1 bit)
STBMOD : Standby Mode
bits : 1 - 1 (1 bit)
WURST : Wakeup Flag Reset
bits : 2 - 2 (1 bit)
STBRST : Standby Flag Reset
bits : 3 - 3 (1 bit)
LVDEN : Low Voltage Detector Enable
bits : 4 - 4 (1 bit)
LVDT : Low Voltage Detector Threshold
bits : 5 - 7 (3 bit)
BKPWEN : Backup Domain Write Enable
bits : 8 - 8 (1 bit)
LDLP : Low-driver mode when use low power LDO.
bits : 10 - 10 (1 bit)
LDNP : Low-driver mode when use normal power LDO
bits : 11 - 11 (1 bit)
LDOVS : LDO output voltage select
bits : 14 - 15 (2 bit)
HDEN : High-driver mode enable
bits : 16 - 16 (1 bit)
HDS : High-driver mode switch
bits : 17 - 17 (1 bit)
LDEN : Low-driver mode enable in Deep-sleep mode
bits : 18 - 19 (2 bit)
power control/status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUF : Wakeup flag
bits : 0 - 0 (1 bit)
access : read-only
STBF : Standby flag
bits : 1 - 1 (1 bit)
access : read-only
LVDF : Low Voltage Detector Status Flag
bits : 2 - 2 (1 bit)
access : read-only
WUPEN : Enable WKUP pin
bits : 8 - 8 (1 bit)
access : read-write
LDOVSRF : LDO voltage select ready flag
bits : 14 - 14 (1 bit)
access : read-only
HDRF : High-driver ready flag
bits : 16 - 16 (1 bit)
access : read-only
HDSRF : High-driver switch ready flag
bits : 17 - 17 (1 bit)
access : read-only
LDRF : Low-driver mode ready flag
bits : 18 - 19 (2 bit)
access : read-write
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