\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRC8MEN : Internal 8MHz RC oscillator Enable
bits : 0 - 0 (1 bit)
access : read-write
IRC8MSTB : IRC8M Internal 8MHz RC Oscillator stabilization Flag
bits : 1 - 1 (1 bit)
access : read-only
IRC8MADJ : Internal 8MHz RC Oscillator clock trim adjust value
bits : 3 - 7 (5 bit)
access : read-write
IRC8MCALIB : Internal 8MHz RC Oscillator calibration value register
bits : 8 - 15 (8 bit)
access : read-only
HXTALEN : External High Speed oscillator Enable
bits : 16 - 16 (1 bit)
access : read-write
HXTALSTB : External crystal oscillator (HXTAL) clock stabilization flag
bits : 17 - 17 (1 bit)
access : read-only
HXTALBPS : External crystal oscillator (HXTAL) clock bypass mode enable
bits : 18 - 18 (1 bit)
access : read-write
CKMEN : HXTAL Clock Monitor Enable
bits : 19 - 19 (1 bit)
access : read-write
PLLEN : PLL enable
bits : 24 - 24 (1 bit)
access : read-write
PLLSTB : PLL Clock Stabilization Flag
bits : 25 - 25 (1 bit)
access : read-only
PLL1EN : PLL1 enable
bits : 26 - 26 (1 bit)
access : read-write
PLL1STB : PLL1 Clock Stabilization Flag
bits : 27 - 27 (1 bit)
access : read-only
PLL2EN : PLL2 enable
bits : 28 - 28 (1 bit)
access : read-write
PLL2STB : PLL2 Clock Stabilization Flag
bits : 29 - 29 (1 bit)
access : read-only
APB1 reset register (RCU_APB1RST)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMER2RST : TIMER2 timer reset
bits : 1 - 1 (1 bit)
TIMER3RST : TIMER3 timer reset
bits : 2 - 2 (1 bit)
TIMER5RST : TIMER5 timer reset
bits : 4 - 4 (1 bit)
TIMER6RST : TIMER6 timer reset
bits : 5 - 5 (1 bit)
TIMER11RST : TIMER11 timer reset
bits : 6 - 6 (1 bit)
TIMER12RST : TIMER12 timer reset
bits : 7 - 7 (1 bit)
TIMER13RST : TIMER13 timer reset
bits : 8 - 8 (1 bit)
WWDGTRST : Window watchdog timer reset
bits : 11 - 11 (1 bit)
SPI1RST : SPI1 reset
bits : 14 - 14 (1 bit)
SPI2RST : SPI2 reset
bits : 15 - 15 (1 bit)
USART1RST : USART1 reset
bits : 17 - 17 (1 bit)
USART2RST : USART2 reset
bits : 18 - 18 (1 bit)
UART3RST : UART3 reset
bits : 19 - 19 (1 bit)
UART4RST : UART4 reset
bits : 20 - 20 (1 bit)
I2C0RST : I2C0 reset
bits : 21 - 21 (1 bit)
I2C1RST : I2C1 reset
bits : 22 - 22 (1 bit)
CAN0RST : CAN0 reset
bits : 25 - 25 (1 bit)
CAN1RST : CAN1 reset
bits : 26 - 26 (1 bit)
BKPIRST : Backup interface reset
bits : 27 - 27 (1 bit)
PMURST : Power control reset
bits : 28 - 28 (1 bit)
DACRST : DAC reset
bits : 29 - 29 (1 bit)
AHB enable register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0EN : DMA0 clock enable
bits : 0 - 0 (1 bit)
DMA1EN : DMA1 clock enable
bits : 1 - 1 (1 bit)
SRAMSPEN : SRAM interface clock enable when sleep mode
bits : 2 - 2 (1 bit)
FMCSPEN : FMC clock enable when sleep mode
bits : 4 - 4 (1 bit)
CRCEN : CRC clock enable
bits : 6 - 6 (1 bit)
EXMCEN : EXMC clock enable
bits : 8 - 8 (1 bit)
SDIOEN : SDIO clock enable
bits : 10 - 10 (1 bit)
USBFSEN : USBFS clock enable
bits : 12 - 12 (1 bit)
APB2 clock enable register (RCU_APB2EN)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AFEN : Alternate function IO clock enable
bits : 0 - 0 (1 bit)
PAEN : GPIO port A clock enable
bits : 2 - 2 (1 bit)
PBEN : GPIO port B clock enable
bits : 3 - 3 (1 bit)
PCEN : GPIO port C clock enable
bits : 4 - 4 (1 bit)
PDEN : GPIO port D clock enable
bits : 5 - 5 (1 bit)
PEEN : GPIO port E clock enable
bits : 6 - 6 (1 bit)
PFEN : GPIO port F clock enable
bits : 7 - 7 (1 bit)
PGEN : GPIO port G clock enable
bits : 8 - 8 (1 bit)
ADC0EN : ADC0 clock enable
bits : 9 - 9 (1 bit)
ADC1EN : ADC1 clock enable
bits : 10 - 10 (1 bit)
TIMER0EN : TIMER0 clock enable
bits : 11 - 11 (1 bit)
SPI0EN : SPI0 clock enable
bits : 12 - 12 (1 bit)
TIMER7EN : TIMER7 clock enable
bits : 13 - 13 (1 bit)
USART0EN : USART0 clock enable
bits : 14 - 14 (1 bit)
ADC2EN : ADC2 clock enable
bits : 15 - 15 (1 bit)
TIMER8EN : TIMER8 clock enable
bits : 19 - 19 (1 bit)
TIMER9EN : TIMER9 clock enable
bits : 20 - 20 (1 bit)
TIMER10EN : TIMER10 clock enable
bits : 21 - 21 (1 bit)
APB1 clock enable register (RCU_APB1EN)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMER2EN : TIMER2 timer clock enable
bits : 1 - 1 (1 bit)
TIMER3EN : TIMER3 timer clock enable
bits : 2 - 2 (1 bit)
TIMER5EN : TIMER5 timer clock enable
bits : 4 - 4 (1 bit)
TIMER6EN : TIMER6 timer clock enable
bits : 5 - 5 (1 bit)
TIMER11EN : TIMER11 timer clock enable
bits : 6 - 6 (1 bit)
TIMER12EN : TIMER12 timer clock enable
bits : 7 - 7 (1 bit)
TIMER13EN : TIMER13 timer clock enable
bits : 8 - 8 (1 bit)
WWDGTEN : Window watchdog timer clock enable
bits : 11 - 11 (1 bit)
SPI1EN : SPI1 clock enable
bits : 14 - 14 (1 bit)
SPI2EN : SPI2 clock enable
bits : 15 - 15 (1 bit)
USART1EN : USART1 clock enable
bits : 17 - 17 (1 bit)
USART2EN : USART2 clock enable
bits : 18 - 18 (1 bit)
UART3EN : UART3 clock enable
bits : 19 - 19 (1 bit)
UART4EN : UART4 clock enable
bits : 20 - 20 (1 bit)
I2C0EN : I2C0 clock enable
bits : 21 - 21 (1 bit)
I2C1EN : I2C1 clock enable
bits : 22 - 22 (1 bit)
CAN0EN : CAN0 clock enable
bits : 25 - 25 (1 bit)
CAN1EN : CAN1 clock enable
bits : 26 - 26 (1 bit)
BKPIEN : Backup interface clock enable
bits : 27 - 27 (1 bit)
PMUEN : Power control clock enable
bits : 28 - 28 (1 bit)
DACEN : DAC clock enable
bits : 29 - 29 (1 bit)
Backup domain control register (RCU_BDCTL)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LXTALEN : LXTAL enable
bits : 0 - 0 (1 bit)
access : read-write
LXTALSTB : External low-speed oscillator stabilization
bits : 1 - 1 (1 bit)
access : read-only
LXTALBPS : LXTAL bypass mode enable
bits : 2 - 2 (1 bit)
access : read-write
LXTALDRI : LXTAL drive capability
bits : 3 - 4 (2 bit)
access : read-write
RTCSRC : RTC clock entry selection
bits : 8 - 9 (2 bit)
access : read-write
RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)
access : read-write
BKPRST : Backup domain reset
bits : 16 - 16 (1 bit)
access : read-write
Reset source /clock register (RCU_RSTSCK)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRC40KEN : IRC40K enable
bits : 0 - 0 (1 bit)
access : read-write
IRC40KSTB : IRC40K stabilization
bits : 1 - 1 (1 bit)
access : read-only
RSTFC : Reset flag clear
bits : 24 - 24 (1 bit)
access : read-write
EPRSTF : External PIN reset flag
bits : 26 - 26 (1 bit)
access : read-only
PORRSTF : Power reset flag
bits : 27 - 27 (1 bit)
access : read-only
SWRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-only
FWDGTRSTF : Free Watchdog timer reset flag
bits : 29 - 29 (1 bit)
access : read-only
WWDGTRSTF : Window watchdog timer reset flag
bits : 30 - 30 (1 bit)
access : read-only
LPRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
access : read-only
AHB reset register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBFSRST : USBFS reset
bits : 12 - 12 (1 bit)
Clock Configuration register 1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREDV0 : PREDV0 division factor
bits : 0 - 3 (4 bit)
PREDV1 : PREDV1 division factor
bits : 4 - 7 (4 bit)
PLL1MF : The PLL1 clock multiplication factor
bits : 8 - 11 (4 bit)
PLL2MF : The PLL2 clock multiplication factor
bits : 12 - 15 (4 bit)
PREDV0SEL : PREDV0 input Clock Source Selection
bits : 16 - 16 (1 bit)
I2S1SEL : I2S1 Clock Source Selection
bits : 17 - 17 (1 bit)
I2S2SEL : I2S2 Clock Source Selection
bits : 18 - 18 (1 bit)
ADCPSC_3 : Bit 4 of ADCPSC
bits : 29 - 29 (1 bit)
PLLPRESEL : PLL Clock Source Selection
bits : 30 - 30 (1 bit)
PLL2MF_4 : Bit 5 of PLL2MF
bits : 31 - 31 (1 bit)
Deep sleep mode Voltage register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSLPVS : Deep-sleep mode voltage select
bits : 0 - 2 (3 bit)
access : read-write
Clock configuration register 0 (RCU_CFG0)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCS : System clock switch
bits : 0 - 1 (2 bit)
access : read-write
SCSS : System clock switch status
bits : 2 - 3 (2 bit)
access : read-only
AHBPSC : AHB prescaler selection
bits : 4 - 7 (4 bit)
access : read-write
APB1PSC : APB1 prescaler selection
bits : 8 - 10 (3 bit)
access : read-write
APB2PSC : APB2 prescaler selection
bits : 11 - 13 (3 bit)
access : read-write
ADCPSC_1_0 : ADC clock prescaler selection
bits : 14 - 15 (2 bit)
access : read-write
PLLSEL : PLL Clock Source Selection
bits : 16 - 16 (1 bit)
access : read-write
PREDV0_LSB : The LSB of PREDV0 division factor
bits : 17 - 17 (1 bit)
access : read-write
PLLMF_3_0 : The PLL clock multiplication factor
bits : 18 - 21 (4 bit)
access : read-write
USBFSPSC_1_0 : USBFS clock prescaler selection
bits : 22 - 23 (2 bit)
access : read-write
CKOUT0SEL : CKOUT0 Clock Source Selection
bits : 24 - 27 (4 bit)
access : read-write
ADCPSC_2 : Bit 2 of ADCPSC
bits : 28 - 28 (1 bit)
access : read-write
PLLMF_5_4 : Bit 5 and Bit 4 of PLLMF
bits : 29 - 30 (2 bit)
access : read-write
USBFSPSC : Bit 2 of USBFSPSC
bits : 31 - 31 (1 bit)
access : read-write
Clock interrupt register (RCU_INT)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRC40KSTBIF : IRC40K stabilization interrupt flag
bits : 0 - 0 (1 bit)
access : read-only
LXTALSTBIF : LXTAL stabilization interrupt flag
bits : 1 - 1 (1 bit)
access : read-only
IRC8MSTBIF : IRC8M stabilization interrupt flag
bits : 2 - 2 (1 bit)
access : read-only
HXTALSTBIF : HXTAL stabilization interrupt flag
bits : 3 - 3 (1 bit)
access : read-only
PLLSTBIF : PLL stabilization interrupt flag
bits : 4 - 4 (1 bit)
access : read-only
PLL1STBIF : PLL1 stabilization interrupt flag
bits : 5 - 5 (1 bit)
access : read-only
PLL2STBIF : PLL2 stabilization interrupt flag
bits : 6 - 6 (1 bit)
access : read-only
CKMIF : HXTAL Clock Stuck Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-only
IRC40KSTBIE : IRC40K Stabilization interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
LXTALSTBIE : LXTAL Stabilization Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
IRC8MSTBIE : IRC8M Stabilization Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
HXTALSTBIE : HXTAL Stabilization Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
PLLSTBIE : PLL Stabilization Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
PLL1STBIE : PLL1 Stabilization Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
PLL2STBIE : PLL2 Stabilization Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
IRC40KSTBIC : IRC40K Stabilization Interrupt Clear
bits : 16 - 16 (1 bit)
access : write-only
LXTALSTBIC : LXTAL Stabilization Interrupt Clear
bits : 17 - 17 (1 bit)
access : write-only
IRC8MSTBIC : IRC8M Stabilization Interrupt Clear
bits : 18 - 18 (1 bit)
access : write-only
HXTALSTBIC : HXTAL Stabilization Interrupt Clear
bits : 19 - 19 (1 bit)
access : write-only
PLLSTBIC : PLL stabilization Interrupt Clear
bits : 20 - 20 (1 bit)
access : write-only
PLL1STBIC : PLL1 stabilization Interrupt Clear
bits : 21 - 21 (1 bit)
access : write-only
PLL2STBIC : PLL2 stabilization Interrupt Clear
bits : 22 - 22 (1 bit)
access : write-only
CKMIC : HXTAL Clock Stuck Interrupt Clear
bits : 23 - 23 (1 bit)
access : write-only
APB2 reset register (RCU_APB2RST)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AFRST : Alternate function I/O reset
bits : 0 - 0 (1 bit)
PARST : GPIO port A reset
bits : 2 - 2 (1 bit)
PBRST : GPIO port B reset
bits : 3 - 3 (1 bit)
PCRST : GPIO port C reset
bits : 4 - 4 (1 bit)
PDRST : GPIO port D reset
bits : 5 - 5 (1 bit)
PERST : GPIO port E reset
bits : 6 - 6 (1 bit)
PFRST : GPIO portF reset
bits : 7 - 7 (1 bit)
PGRST : GPIO port G reset
bits : 8 - 8 (1 bit)
ADC0RST : ADC0 reset
bits : 9 - 9 (1 bit)
ADC1RST : ADC1 reset
bits : 10 - 10 (1 bit)
TIMER0RST : Timer 0 reset
bits : 11 - 11 (1 bit)
SPI0RST : SPI0 reset
bits : 12 - 12 (1 bit)
TIMER7RST : Timer 7 reset
bits : 13 - 13 (1 bit)
USART0RST : USART0 Reset
bits : 14 - 14 (1 bit)
ADC2RST : ADC2 reset
bits : 15 - 15 (1 bit)
TIMER8RST : Timer 8 reset
bits : 19 - 19 (1 bit)
TIMER9RST : Timer 9 reset
bits : 20 - 20 (1 bit)
TIMER10RST : Timer 10 reset
bits : 21 - 21 (1 bit)
Additional clock control register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CK48MSEL : 48MHz clock selection
bits : 0 - 0 (1 bit)
access : read-write
IRC48MEN : Internal 48MHz RC oscillator enable
bits : 16 - 16 (1 bit)
access : read-write
IRC48MSTB : Internal 48MHz RC oscillator clock stabilization Flag
bits : 17 - 17 (1 bit)
access : read-only
IRC48MCALIB : Internal 48MHz RC oscillator calibration value register
bits : 24 - 31 (8 bit)
access : read-only
Additional clock interrupt register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRC48MSTBIF : IRC48M stabilization interrupt flag
bits : 6 - 6 (1 bit)
access : read-only
IRC48MSTBIE : Internal 48 MHz RC oscillator Stabilization Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
IRC48MSTBIC : Internal 48 MHz RC oscillator Stabilization Interrupt Clear
bits : 22 - 22 (1 bit)
access : write
APB1 additional reset register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTCRST : CTC reset
bits : 27 - 27 (1 bit)
access : read-write
APB1 additional enable register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTCEN : CTC clock enable
bits : 27 - 27 (1 bit)
access : read-write
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