\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Counter enable
bits : 0 - 0 (1 bit)
UPDIS : Update disable
bits : 1 - 1 (1 bit)
UPS : Update source
bits : 2 - 2 (1 bit)
SPM : Single pulse mode
bits : 3 - 3 (1 bit)
DIR : Direction
bits : 4 - 4 (1 bit)
CAM : Counter aligns mode selection
bits : 5 - 6 (2 bit)
ARSE : Auto-reload shadow enable
bits : 7 - 7 (1 bit)
CKDIV : Clock division
bits : 8 - 9 (2 bit)
Interrupt flag register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPIF : Update interrupt flag
bits : 0 - 0 (1 bit)
CH0IF : Channel 0 capture/compare interrupt flag
bits : 1 - 1 (1 bit)
CH1IF : Channel 1 capture/compare interrupt flag
bits : 2 - 2 (1 bit)
CH2IF : Channel 2 capture/compare interrupt flag
bits : 3 - 3 (1 bit)
CH3IF : Channel 3 capture/compare interrupt flag
bits : 4 - 4 (1 bit)
CMTIF : Channel commutation interrupt flag
bits : 5 - 5 (1 bit)
TRGIF : Trigger interrupt flag
bits : 6 - 6 (1 bit)
BRKIF : Break interrupt flag
bits : 7 - 7 (1 bit)
CH0OF : Channel 0 over capture flag
bits : 9 - 9 (1 bit)
CH1OF : Channel 1 over capture flag
bits : 10 - 10 (1 bit)
CH2OF : Channel 2 over capture flag
bits : 11 - 11 (1 bit)
CH3OF : Channel 3 over capture flag
bits : 12 - 12 (1 bit)
Software event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UPG : Update event generation
bits : 0 - 0 (1 bit)
CH0G : Channel 0 capture or compare event generation
bits : 1 - 1 (1 bit)
CH1G : Channel 1 capture or compare event generation
bits : 2 - 2 (1 bit)
CH2G : Channel 2 capture or compare event generation
bits : 3 - 3 (1 bit)
CH3G : Channel 3 capture or compare event generation
bits : 4 - 4 (1 bit)
CMTG : Channel commutation event generation
bits : 5 - 5 (1 bit)
TRGG : Trigger event generation
bits : 6 - 6 (1 bit)
BRKG : Break event generation
bits : 7 - 7 (1 bit)
Channel control register 0 (output mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0MS : Channel 0 I/O mode selection
bits : 0 - 1 (2 bit)
CH0COMFEN : Channel 0 output compare fast enable
bits : 2 - 2 (1 bit)
CH0COMSEN : Channel 0 compare output shadow enable
bits : 3 - 3 (1 bit)
CH0COMCTL : Channel 0 compare output control
bits : 4 - 6 (3 bit)
CH0COMCEN : Channel 0 output compare clear enable
bits : 7 - 7 (1 bit)
CH1MS : Channel 1 mode selection
bits : 8 - 9 (2 bit)
CH1COMFEN : Channel 1 output compare fast enable
bits : 10 - 10 (1 bit)
CH1COMSEN : Channel 1 output compare shadow enable
bits : 11 - 11 (1 bit)
CH1COMCTL : Channel 1 compare output control
bits : 12 - 14 (3 bit)
CH1COMCEN : Channel 1 output compare clear enable
bits : 15 - 15 (1 bit)
Channel control register 0 (input mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CHCTL0_Output
reset_Mask : 0x0
CH0MS : Channel 0 mode selection
bits : 0 - 1 (2 bit)
CH0CAPPSC : Channel 0 input capture prescaler
bits : 2 - 3 (2 bit)
CH0CAPFLT : Channel 0 input capture filter control
bits : 4 - 7 (4 bit)
CH1MS : Channel 1 mode selection
bits : 8 - 9 (2 bit)
CH1CAPPSC : Channel 1 input capture prescaler
bits : 10 - 11 (2 bit)
CH1CAPFLT : Channel 1 input capture filter control
bits : 12 - 15 (4 bit)
Channel control register 1 (output mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2MS : Channel 2 I/O mode selection
bits : 0 - 1 (2 bit)
CH2COMFEN : Channel 2 output compare fast enable
bits : 2 - 2 (1 bit)
CH2COMSEN : Channel 2 compare output shadow enable
bits : 3 - 3 (1 bit)
CH2COMCTL : Channel 2 compare output control
bits : 4 - 6 (3 bit)
CH2COMCEN : Channel 2 output compare clear enable
bits : 7 - 7 (1 bit)
CH3MS : Channel 3 mode selection
bits : 8 - 9 (2 bit)
CH3COMFEN : Channel 3 output compare fast enable
bits : 10 - 10 (1 bit)
CH3COMSEN : Channel 3 output compare shadow enable
bits : 11 - 11 (1 bit)
CH3COMCTL : Channel 3 compare output control
bits : 12 - 14 (3 bit)
CH3COMCEN : Channel 3 output compare clear enable
bits : 15 - 15 (1 bit)
Channel control register 1 (input mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CHCTL1_Output
reset_Mask : 0x0
CH2MS : Channel 2 mode selection
bits : 0 - 1 (2 bit)
CH2CAPPSC : Channel 2 input capture prescaler
bits : 2 - 3 (2 bit)
CH2CAPFLT : Channel 2 input capture filter control
bits : 4 - 7 (4 bit)
CH3MS : Channel 3 mode selection
bits : 8 - 9 (2 bit)
CH3CAPPSC : Channel 3 input capture prescaler
bits : 10 - 11 (2 bit)
CH3CAPFLT : Channel 3 input capture filter control
bits : 12 - 15 (4 bit)
Channel control register 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0EN : Channel 0 capture/compare function enable
bits : 0 - 0 (1 bit)
CH0P : Channel 0 capture/compare function polarity
bits : 1 - 1 (1 bit)
CH0NEN : Channel 0 complementary output enable
bits : 2 - 2 (1 bit)
CH0NP : Channel 0 complementary output polarity
bits : 3 - 3 (1 bit)
CH1EN : Channel 1 capture/compare function enable
bits : 4 - 4 (1 bit)
CH1P : Channel 1 capture/compare function polarity
bits : 5 - 5 (1 bit)
CH1NEN : Channel 1 complementary output enable
bits : 6 - 6 (1 bit)
CH1NP : Channel 1 complementary output polarity
bits : 7 - 7 (1 bit)
CH2EN : Channel 2 capture/compare function enable
bits : 8 - 8 (1 bit)
CH2P : Channel 2 capture/compare function polarity
bits : 9 - 9 (1 bit)
CH2NEN : Channel 2 complementary output enable
bits : 10 - 10 (1 bit)
CH2NP : Channel 2 complementary output polarity
bits : 11 - 11 (1 bit)
CH3EN : Channel 3 capture/compare function enable
bits : 12 - 12 (1 bit)
CH3P : Channel 3 capture/compare function polarity
bits : 13 - 13 (1 bit)
counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : current counter value
bits : 0 - 15 (16 bit)
prescaler
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : Prescaler value of the counter clock
bits : 0 - 15 (16 bit)
Counter auto reload register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CARL : Counter auto reload value
bits : 0 - 15 (16 bit)
Counter repetition register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CREP : Counter repetition value
bits : 0 - 7 (8 bit)
Channel 0 capture/compare value register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0VAL : Capture or compare value of channel0
bits : 0 - 15 (16 bit)
Channel 1 capture/compare value register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1VAL : Capture or compare value of channel1
bits : 0 - 15 (16 bit)
Channel 2 capture/compare value register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2VAL : Capture or compare value of channel 2
bits : 0 - 15 (16 bit)
control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCSE : Commutation control shadow enable
bits : 0 - 0 (1 bit)
CCUC : Commutation control shadow register update control
bits : 2 - 2 (1 bit)
DMAS : DMA request source selection
bits : 3 - 3 (1 bit)
MMC : Master mode control
bits : 4 - 6 (3 bit)
TI0S : Channel 0 trigger input selection
bits : 7 - 7 (1 bit)
ISO0 : Idle state of channel 0 output
bits : 8 - 8 (1 bit)
ISO0N : Idle state of channel 0 complementary output
bits : 9 - 9 (1 bit)
ISO1 : Idle state of channel 1 output
bits : 10 - 10 (1 bit)
ISO1N : Idle state of channel 1 complementary output
bits : 11 - 11 (1 bit)
ISO2 : Idle state of channel 2 output
bits : 12 - 12 (1 bit)
ISO2N : Idle state of channel 2 complementary output
bits : 13 - 13 (1 bit)
ISO3 : Idle state of channel 3 output
bits : 14 - 14 (1 bit)
Channel 3 capture/compare value register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3VAL : Capture or compare value of channel 3
bits : 0 - 15 (16 bit)
channel complementary protection register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCFG : Dead time configure
bits : 0 - 7 (8 bit)
PROT : Complementary register protect control
bits : 8 - 9 (2 bit)
IOS : Idle mode off-state configure
bits : 10 - 10 (1 bit)
ROS : Run mode off-state configure
bits : 11 - 11 (1 bit)
BRKEN : Break enable
bits : 12 - 12 (1 bit)
BRKP : Break polarity
bits : 13 - 13 (1 bit)
OAEN : Output automatic enable
bits : 14 - 14 (1 bit)
POEN : Primary output enable
bits : 15 - 15 (1 bit)
DMA configuration register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMATA : DMA transfer access start address
bits : 0 - 4 (5 bit)
DMATC : DMA transfer count
bits : 8 - 12 (5 bit)
DMA transfer buffer register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMATB : DMA transfer buffer
bits : 0 - 15 (16 bit)
slave mode configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMC : Slave mode selection
bits : 0 - 2 (3 bit)
TRGS : Trigger selection
bits : 4 - 6 (3 bit)
MSM : Master/Slave mode
bits : 7 - 7 (1 bit)
ETFC : External trigger filter control
bits : 8 - 11 (4 bit)
ETPSC : External trigger prescaler
bits : 12 - 13 (2 bit)
SMC1 : Part of SMC for enable External clock mode1
bits : 14 - 14 (1 bit)
ETP : External trigger polarity
bits : 15 - 15 (1 bit)
DMA/Interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPIE : Update interrupt enable
bits : 0 - 0 (1 bit)
CH0IE : Channel 0 capture/compare interrupt enable
bits : 1 - 1 (1 bit)
CH1IE : Channel 1 capture/compare interrupt enable
bits : 2 - 2 (1 bit)
CH2IE : Channel 2 capture/compare interrupt enable
bits : 3 - 3 (1 bit)
CH3IE : Channel 3 capture/compare interrupt enable
bits : 4 - 4 (1 bit)
CMTIE : commutation interrupt enable
bits : 5 - 5 (1 bit)
TRGIE : Trigger interrupt enable
bits : 6 - 6 (1 bit)
BRKIE : Break interrupt enable
bits : 7 - 7 (1 bit)
UPDEN : Update DMA request enable
bits : 8 - 8 (1 bit)
CH0DEN : Channel 0 capture/compare DMA request enable
bits : 9 - 9 (1 bit)
CH1DEN : Channel 1 capture/compare DMA request enable
bits : 10 - 10 (1 bit)
CH2DEN : Channel 2 capture/compare DMA request enable
bits : 11 - 11 (1 bit)
CH3DEN : Channel 3 capture/compare DMA request enable
bits : 12 - 12 (1 bit)
CMTDEN : Commutation DMA request enable
bits : 13 - 13 (1 bit)
TRGDEN : Trigger DMA request enable
bits : 14 - 14 (1 bit)
Configuration register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTSEL : The output value selection
bits : 0 - 0 (1 bit)
CHVSEL : Write CHxVAL register selection
bits : 1 - 1 (1 bit)
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