\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Counter enable
bits : 0 - 0 (1 bit)
UPDIS : Update disable
bits : 1 - 1 (1 bit)
UPS : Update source
bits : 2 - 2 (1 bit)
SPM : Single pulse mode
bits : 3 - 3 (1 bit)
ARSE : Auto-reload shadow enable
bits : 7 - 7 (1 bit)
CKDIV : Clock division
bits : 8 - 9 (2 bit)
interrupt flag register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPIF : Update interrupt flag
bits : 0 - 0 (1 bit)
CH0IF : Channel 0 capture/compare interrupt flag
bits : 1 - 1 (1 bit)
CH1IF : Channel 1 capture/compare interrupt flag
bits : 2 - 2 (1 bit)
TRGIF : Trigger interrupt flag
bits : 6 - 6 (1 bit)
CH0OF : Channel 0 over capture flag
bits : 9 - 9 (1 bit)
CH1OF : Channel 1 over capture flag
bits : 10 - 10 (1 bit)
event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UPG : Update generation
bits : 0 - 0 (1 bit)
CH0G : Channel 0 capture or compare event generation
bits : 1 - 1 (1 bit)
CH1G : Channel 1 capture or compare event generation
bits : 2 - 2 (1 bit)
TRGG : Trigger event generation
bits : 6 - 6 (1 bit)
Channel control register 0 (output mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0MS : Channel 0 I/O mode selection
bits : 0 - 1 (2 bit)
CH0COMFEN : Channel 0 output compare fast enable
bits : 2 - 2 (1 bit)
CH0COMSEN : Channel 0 compare output shadow enable
bits : 3 - 3 (1 bit)
CH0COMCTL : Channel 0 compare output control
bits : 4 - 6 (3 bit)
CH1MS : Channel 1 mode selection
bits : 8 - 9 (2 bit)
CH1COMFEN : Channel 1 output compare fast enable
bits : 10 - 10 (1 bit)
CH1COMSEN : Channel 1 output compare shadow enable
bits : 11 - 11 (1 bit)
CH1COMCTL : Channel 1 compare output control
bits : 12 - 14 (3 bit)
Channel control register 0 (input mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CHCTL0_Output
reset_Mask : 0x0
CH0MS : Channel 0 mode selection
bits : 0 - 1 (2 bit)
CH0CAPPSC : Channel 0 input capture prescaler
bits : 2 - 3 (2 bit)
CH0CAPFLT : Channel 0 input capture filter control
bits : 4 - 7 (4 bit)
CH1MS : Channel 1 mode selection
bits : 8 - 9 (2 bit)
CH1CAPPSC : Channel 1 input capture prescaler
bits : 10 - 11 (2 bit)
CH1CAPFLT : Channel 1 input capture filter control
bits : 12 - 15 (4 bit)
Channel control register 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0EN : Channel 0 capture/compare function enable
bits : 0 - 0 (1 bit)
CH0P : Channel 0 capture/compare function polarity
bits : 1 - 1 (1 bit)
CH0NP : Channel 0 complementary output polarity
bits : 3 - 3 (1 bit)
CH1EN : Channel 1 capture/compare function enable
bits : 4 - 4 (1 bit)
CH1P : Channel 1 capture/compare function polarity
bits : 5 - 5 (1 bit)
CH1NP : Channel 1 complementary output polarity
bits : 7 - 7 (1 bit)
Counter register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : current counter value
bits : 0 - 15 (16 bit)
Prescaler register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : Prescaler value of the counter clock
bits : 0 - 15 (16 bit)
Counter auto reload register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CARL : Counter auto reload value
bits : 0 - 15 (16 bit)
Channel 0 capture/compare value register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0VAL : Capture or compare value of channel0
bits : 0 - 15 (16 bit)
Channel 1 capture/compare value register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1VAL : Capture or compare value of channel1
bits : 0 - 15 (16 bit)
slave mode configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMC : Slave mode control
bits : 0 - 2 (3 bit)
TRGS : Trigger selection
bits : 4 - 6 (3 bit)
MSM : Master-slave mode
bits : 7 - 7 (1 bit)
DMA and interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPIE : Update interrupt enable
bits : 0 - 0 (1 bit)
CH0IE : Channel 0 capture/compare interrupt enable
bits : 1 - 1 (1 bit)
CH1IE : Channel 1 capture/compare interrupt enable
bits : 2 - 2 (1 bit)
TRGIE : Trigger interrupt enable
bits : 6 - 6 (1 bit)
configuration register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHVSEL : Write CHxVAL register selection
bits : 1 - 1 (1 bit)
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