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TIMER

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTL0

INTF

SWEVG

CHCTL0_Output

CHCTL0_Input

CHCTL2

CNT

PSC

CAR

CH0CV

IRMP

DMAINTEN

CFG


CTL0

control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL0 CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN UPDIS UPS ARSE CKDIV

CEN : Counter enable
bits : 0 - 0 (1 bit)

UPDIS : Update disable
bits : 1 - 1 (1 bit)

UPS : Update source
bits : 2 - 2 (1 bit)

ARSE : Auto-reload shadow enable
bits : 7 - 7 (1 bit)

CKDIV : Clock division
bits : 8 - 9 (2 bit)


INTF

interrupt flag register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTF INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPIF CH0IF CH0OF

UPIF : Update interrupt flag
bits : 0 - 0 (1 bit)

CH0IF : Channel 0 capture/compare interrupt flag
bits : 1 - 1 (1 bit)

CH0OF : Channel 0 over capture flag
bits : 9 - 9 (1 bit)


SWEVG

event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWEVG SWEVG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPG CH0G

UPG : Update generation
bits : 0 - 0 (1 bit)

CH0G : Channel 0 capture or compare event generation
bits : 1 - 1 (1 bit)


CHCTL0_Output

Channel control register 0 (output mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTL0_Output CHCTL0_Output read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0MS CH0COMFEN CH0COMSEN CH0COMCTL

CH0MS : Channel 0 I/O mode selection
bits : 0 - 1 (2 bit)

CH0COMFEN : Channel 0 output compare fast enable
bits : 2 - 2 (1 bit)

CH0COMSEN : Channel 0 compare output shadow enable
bits : 3 - 3 (1 bit)

CH0COMCTL : Channel 0 compare output control
bits : 4 - 6 (3 bit)


CHCTL0_Input

Channel control register 0 ( (input mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CHCTL0_Output
reset_Mask : 0x0

CHCTL0_Input CHCTL0_Input read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0MS CH0CAPPSC CH0CAPFLT

CH0MS : Channel 0 mode selection
bits : 0 - 1 (2 bit)

CH0CAPPSC : Channel 0 input capture prescaler
bits : 2 - 3 (2 bit)

CH0CAPFLT : Channel 0 input capture filter control
bits : 4 - 7 (4 bit)


CHCTL2

Channel control register 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTL2 CHCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0EN CH0P CH0NP

CH0EN : Channel 0 capture/compare function enable
bits : 0 - 0 (1 bit)

CH0P : Channel 0 capture/compare polarity
bits : 1 - 1 (1 bit)

CH0NP : Channel 0 complementary output polarity
bits : 3 - 3 (1 bit)


CNT

Counter register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : current counter value
bits : 0 - 15 (16 bit)


PSC

Prescaler register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSC PSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC

PSC : Prescaler value of the counter clock
bits : 0 - 15 (16 bit)


CAR

Counter auto reload register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAR CAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARL

CARL : Counter auto reload value
bits : 0 - 15 (16 bit)


CH0CV

Channel 0 capture/compare value register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0CV CH0CV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0VAL

CH0VAL : Capture or compare value of channel 0
bits : 0 - 15 (16 bit)


IRMP

channel input remap register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRMP IRMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ITI1_RMP

ITI1_RMP : Internal trigger input1 remap
bits : 10 - 11 (2 bit)


DMAINTEN

DMA/Interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAINTEN DMAINTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPIE CH0IE

UPIE : Update interrupt enable
bits : 0 - 0 (1 bit)

CH0IE : Channel 0 capture/compare interrupt enable
bits : 1 - 1 (1 bit)


CFG

configuration register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHVSEL

CHVSEL : Write CHxVAL register selection
bits : 1 - 1 (1 bit)



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