\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Global OTG control and status register (USBFS_GOTGCS)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRPS : SRP success
bits : 0 - 0 (1 bit)
access : read-only
SRPREQ : SRP request
bits : 1 - 1 (1 bit)
access : read-write
HNPS : Host success
bits : 8 - 8 (1 bit)
access : read-only
HNPREQ : HNP request
bits : 9 - 9 (1 bit)
access : read-write
HHNPEN : Host HNP enable
bits : 10 - 10 (1 bit)
access : read-write
DHNPEN : Device HNP enabled
bits : 11 - 11 (1 bit)
access : read-write
IDPS : ID pin status
bits : 16 - 16 (1 bit)
access : read-only
DI : Debounce interval
bits : 17 - 17 (1 bit)
access : read-only
ASV : A-session valid
bits : 18 - 18 (1 bit)
access : read-only
BSV : B-session valid
bits : 19 - 19 (1 bit)
access : read-only
Global reset control register (USBFS_GRSTCTL)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSRST : Core soft reset
bits : 0 - 0 (1 bit)
access : read-write
HCSRST : HCLK soft reset
bits : 1 - 1 (1 bit)
access : read-write
HFCRST : Host frame counter reset
bits : 2 - 2 (1 bit)
access : read-write
RXFF : RxFIFO flush
bits : 4 - 4 (1 bit)
access : read-write
TXFF : TxFIFO flush
bits : 5 - 5 (1 bit)
access : read-write
TXFNUM : TxFIFO number
bits : 6 - 10 (5 bit)
access : read-write
Host periodic transmit FIFO length register (HPTFLEN)
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPTXFSAR : Host periodic TxFIFO start address
bits : 0 - 15 (16 bit)
HPTXFD : Host periodic TxFIFO depth
bits : 16 - 31 (16 bit)
device IN endpoint transmit FIFO size register (DIEP1TFLEN)
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IEPTXRSAR : IN endpoint FIFO transmit RAM start address
bits : 0 - 15 (16 bit)
IEPTXFD : IN endpoint TxFIFO depth
bits : 16 - 31 (16 bit)
device IN endpoint transmit FIFO size register (DIEP2TFLEN)
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IEPTXRSAR : IN endpoint FIFO transmit RAM start address
bits : 0 - 15 (16 bit)
IEPTXFD : IN endpoint TxFIFO depth
bits : 16 - 31 (16 bit)
device IN endpoint transmit FIFO size register (FS_DIEP3TXFLEN)
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IEPTXRSAR : IN endpoint FIFO4 transmit RAM start address
bits : 0 - 15 (16 bit)
IEPTXFD : IN endpoint TxFIFO depth
bits : 16 - 31 (16 bit)
Global interrupt flag register (USBFS_GINTF)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COPM : Current operation mode
bits : 0 - 0 (1 bit)
access : read-only
MFIF : Mode fault interrupt flag
bits : 1 - 1 (1 bit)
access : read-write
OTGIF : OTG interrupt flag
bits : 2 - 2 (1 bit)
access : read-only
SOF : Start of frame
bits : 3 - 3 (1 bit)
access : read-write
RXFNEIF : RxFIFO non-empty interrupt flag
bits : 4 - 4 (1 bit)
access : read-only
NPTXFEIF : Non-periodic TxFIFO empty interrupt flag
bits : 5 - 5 (1 bit)
access : read-only
GNPINAK : Global Non-Periodic IN NAK effective
bits : 6 - 6 (1 bit)
access : read-only
GONAK : Global OUT NAK effective
bits : 7 - 7 (1 bit)
access : read-only
ESP : Early suspend
bits : 10 - 10 (1 bit)
access : read-write
SP : USB suspend
bits : 11 - 11 (1 bit)
access : read-write
RST : USB reset
bits : 12 - 12 (1 bit)
access : read-write
ENUMF : Enumeration finished
bits : 13 - 13 (1 bit)
access : read-write
ISOOPDIF : Isochronous OUT packet dropped interrupt
bits : 14 - 14 (1 bit)
access : read-write
EOPFIF : End of periodic frame interrupt flag
bits : 15 - 15 (1 bit)
access : read-write
IEPIF : IN endpoint interrupt flag
bits : 18 - 18 (1 bit)
access : read-only
OEPIF : OUT endpoint interrupt flag
bits : 19 - 19 (1 bit)
access : read-only
ISOINCIF : Isochronous IN transfer Not Complete Interrupt Flag
bits : 20 - 20 (1 bit)
access : read-write
PXNCIF_ISOONCIF : periodic transfer not complete interrupt flag(Host mode)/isochronous OUT transfer not complete interrupt flag(Device mode)
bits : 21 - 21 (1 bit)
access : read-write
HPIF : Host port interrupt flag
bits : 24 - 24 (1 bit)
access : read-only
HCIF : Host channels interrupt flag
bits : 25 - 25 (1 bit)
access : read-only
PTXFEIF : Periodic TxFIFO empty interrupt flag
bits : 26 - 26 (1 bit)
access : read-only
IDPSC : ID pin status change
bits : 28 - 28 (1 bit)
access : read-write
DISCIF : Disconnect interrupt flag
bits : 29 - 29 (1 bit)
access : read-write
SESIF : Session interrupt flag
bits : 30 - 30 (1 bit)
access : read-write
WKUPIF : Wakeup interrupt flag
bits : 31 - 31 (1 bit)
access : read-write
Global interrupt enable register (USBFS_GINTEN)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFIE : Mode fault interrupt enable
bits : 1 - 1 (1 bit)
access : read-write
OTGIE : OTG interrupt enable
bits : 2 - 2 (1 bit)
access : read-write
SOFIE : Start of frame interrupt enable
bits : 3 - 3 (1 bit)
access : read-write
RXFNEIE : Receive FIFO non-empty interrupt enable
bits : 4 - 4 (1 bit)
access : read-write
NPTXFEIE : Non-periodic TxFIFO empty interrupt enable
bits : 5 - 5 (1 bit)
access : read-write
GNPINAKIE : Global non-periodic IN NAK effective interrupt enable
bits : 6 - 6 (1 bit)
access : read-write
GONAKIE : Global OUT NAK effective interrupt enable
bits : 7 - 7 (1 bit)
access : read-write
ESPIE : Early suspend interrupt enable
bits : 10 - 10 (1 bit)
access : read-write
SPIE : USB suspend interrupt enable
bits : 11 - 11 (1 bit)
access : read-write
RSTIE : USB reset interrupt enable
bits : 12 - 12 (1 bit)
access : read-write
ENUMFIE : Enumeration finish interrupt enable
bits : 13 - 13 (1 bit)
access : read-write
ISOOPDIE : Isochronous OUT packet dropped interrupt enable
bits : 14 - 14 (1 bit)
access : read-write
EOPFIE : End of periodic frame interrupt enable
bits : 15 - 15 (1 bit)
access : read-write
IEPIE : IN endpoints interrupt enable
bits : 18 - 18 (1 bit)
access : read-write
OEPIE : OUT endpoints interrupt enable
bits : 19 - 19 (1 bit)
access : read-write
ISOINCIE : isochronous IN transfer not complete interrupt enable
bits : 20 - 20 (1 bit)
access : read-write
PXNCIE_ISOONCIE : periodic transfer not compelete Interrupt enable(Host mode)/isochronous OUT transfer not complete interrupt enable(Device mode)
bits : 21 - 21 (1 bit)
access : read-write
HPIE : Host port interrupt enable
bits : 24 - 24 (1 bit)
access : read-only
HCIE : Host channels interrupt enable
bits : 25 - 25 (1 bit)
access : read-write
PTXFEIE : Periodic TxFIFO empty interrupt enable
bits : 26 - 26 (1 bit)
access : read-write
IDPSCIE : ID pin status change interrupt enable
bits : 28 - 28 (1 bit)
access : read-write
DISCIE : Disconnect interrupt enable
bits : 29 - 29 (1 bit)
access : read-write
SESIE : Session interrupt enable
bits : 30 - 30 (1 bit)
access : read-write
WKUPIE : Wakeup interrupt enable
bits : 31 - 31 (1 bit)
access : read-write
Global Receive status read(Device mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPNUM : Endpoint number
bits : 0 - 3 (4 bit)
BCOUNT : Byte count
bits : 4 - 14 (11 bit)
DPID : Data PID
bits : 15 - 16 (2 bit)
RPCKST : Recieve packet status
bits : 17 - 20 (4 bit)
Global Receive status read(Host mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : GRSTATR_Device
reset_Mask : 0x0
CNUM : Channel number
bits : 0 - 3 (4 bit)
BCOUNT : Byte count
bits : 4 - 14 (11 bit)
DPID : Data PID
bits : 15 - 16 (2 bit)
RPCKST : Reivece packet status
bits : 17 - 20 (4 bit)
Global Receive status pop(Device mode)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPNUM : Endpoint number
bits : 0 - 3 (4 bit)
BCOUNT : Byte count
bits : 4 - 14 (11 bit)
DPID : Data PID
bits : 15 - 16 (2 bit)
RPCKST : Recieve packet status
bits : 17 - 20 (4 bit)
Global Receive status pop(Host mode)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : GRSTATP_Device
reset_Mask : 0x0
CNUM : Channel number
bits : 0 - 3 (4 bit)
BCOUNT : Byte count
bits : 4 - 14 (11 bit)
DPID : Data PID
bits : 15 - 16 (2 bit)
RPCKST : Reivece packet status
bits : 17 - 20 (4 bit)
Global Receive FIFO size register (USBFS_GRFLEN)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXFD : Rx FIFO depth
bits : 0 - 15 (16 bit)
Host non-periodic transmit FIFO length register (Host mode)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HNPTXRSAR : host non-periodic transmit Tx RAM start address
bits : 0 - 15 (16 bit)
HNPTXFD : host non-periodic TxFIFO depth
bits : 16 - 31 (16 bit)
Device IN endpoint 0 transmit FIFO length (Device mode)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : HNPTFLEN
reset_Mask : 0x0
IEP0TXFD : in endpoint 0 Tx FIFO depth
bits : 0 - 15 (16 bit)
IEP0TXRSAR : in endpoint 0 Tx RAM start address
bits : 16 - 31 (16 bit)
Host non-periodic transmit FIFO/queue status register (HNPTFQSTAT)
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NPTXFS : Non-periodic TxFIFO space
bits : 0 - 15 (16 bit)
NPTXRQS : Non-periodic transmit request queue space
bits : 16 - 23 (8 bit)
NPTXRQTOP : Top of the non-periodic transmit request queue
bits : 24 - 30 (7 bit)
Global core configuration register (USBFS_GCCFG)
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWRON : Power on
bits : 16 - 16 (1 bit)
VBUSACEN : The VBUS A-device Comparer enable
bits : 18 - 18 (1 bit)
VBUSBCEN : The VBUS B-device Comparer enable
bits : 19 - 19 (1 bit)
SOFOEN : SOF output enable
bits : 20 - 20 (1 bit)
VBUSIG : VBUS ignored
bits : 21 - 21 (1 bit)
core ID register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CID : Core ID
bits : 0 - 31 (32 bit)
Global OTG interrupt flag register (USBFS_GOTGINTF)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SESEND : Session end
bits : 2 - 2 (1 bit)
SRPEND : Session request success status change
bits : 8 - 8 (1 bit)
HNPEND : HNP end
bits : 9 - 9 (1 bit)
HNPDET : Host negotiation request detected
bits : 17 - 17 (1 bit)
ADTO : A-device timeout
bits : 18 - 18 (1 bit)
DF : Debounce finish
bits : 19 - 19 (1 bit)
Global AHB control and status register (USBFS_GAHBCS)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GINTEN : Global interrupt enable
bits : 0 - 0 (1 bit)
TXFTH : Tx FIFO threshold
bits : 7 - 7 (1 bit)
PTXFTH : Periodic Tx FIFO threshold
bits : 8 - 8 (1 bit)
Global USB control and status register (OTG_FS_GUSBCSR)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOC : Timeout calibration
bits : 0 - 2 (3 bit)
access : read-write
SRPCEN : SRP capability enable
bits : 8 - 8 (1 bit)
access : read-write
HNPCEN : HNP capability enable
bits : 9 - 9 (1 bit)
access : read-write
UTT : USB turnaround time
bits : 10 - 13 (4 bit)
access : read-write
FHM : Force host mode
bits : 29 - 29 (1 bit)
access : read-write
FDM : Force device mode
bits : 30 - 30 (1 bit)
access : read-write
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