\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
host configuration register (HCTL)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : clock select for USB clock
bits : 0 - 1 (2 bit)
access : read-write
Host periodic transmit FIFO/queue status register (HPTFQSTAT)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTXFS : Periodic transmit data FIFO space available
bits : 0 - 15 (16 bit)
access : read-only
PTXREQS : Periodic transmit request queue space available
bits : 16 - 23 (8 bit)
access : read-only
PTXREQT : Top of the periodic transmit request queue
bits : 24 - 31 (8 bit)
access : read-only
host channel-0 characteristics register (HCH0CTL)
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPL : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSD : Low-speed device
bits : 17 - 17 (1 bit)
EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)
DAR : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CDIS : Channel disable
bits : 30 - 30 (1 bit)
CEN : Channel enable
bits : 31 - 31 (1 bit)
host channel-0 interrupt register (USBFS_HCHxINTF)
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF : Transfer finished
bits : 0 - 0 (1 bit)
CH : Channel halted
bits : 1 - 1 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
USBER : USB bus error
bits : 7 - 7 (1 bit)
BBER : Babble error
bits : 8 - 8 (1 bit)
REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)
DTER : Data toggle error
bits : 10 - 10 (1 bit)
host channel-0 interrupt enable register (HCH0INTEN)
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transfer completed interrupt enable
bits : 0 - 0 (1 bit)
CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)
STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)
NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)
ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)
USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)
BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)
REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)
DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)
host channel-0 transfer length register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLEN : Transfer length
bits : 0 - 18 (19 bit)
PCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
host channel-1 characteristics register (HCH1CTL)
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPL : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSD : Low-speed device
bits : 17 - 17 (1 bit)
EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)
DAR : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CDIS : Channel disable
bits : 30 - 30 (1 bit)
CEN : Channel enable
bits : 31 - 31 (1 bit)
host channel-1 interrupt register (HCH1INTF)
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF : Transfer finished
bits : 0 - 0 (1 bit)
CH : Channel halted
bits : 1 - 1 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
USBER : USB bus error
bits : 7 - 7 (1 bit)
BBER : Babble error
bits : 8 - 8 (1 bit)
REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)
DTER : Data toggle error
bits : 10 - 10 (1 bit)
host channel-1 interrupt enable register (HCH1INTEN)
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transfer completed interrupt enable
bits : 0 - 0 (1 bit)
CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)
STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)
NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)
ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)
USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)
BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)
REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)
DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)
host channel-1 transfer length register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLEN : Transfer length
bits : 0 - 18 (19 bit)
PCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
Host all channels interrupt register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HACHINT : Host all channel interrupts
bits : 0 - 7 (8 bit)
host channel-2 characteristics register (HCH2CTL)
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPL : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSD : Low-speed device
bits : 17 - 17 (1 bit)
EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)
DAR : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CDIS : Channel disable
bits : 30 - 30 (1 bit)
CEN : Channel enable
bits : 31 - 31 (1 bit)
host channel-2 interrupt register (HCH2INTF)
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF : Transfer finished
bits : 0 - 0 (1 bit)
CH : Channel halted
bits : 1 - 1 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
USBER : USB bus error
bits : 7 - 7 (1 bit)
BBER : Babble error
bits : 8 - 8 (1 bit)
REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)
DTER : Data toggle error
bits : 10 - 10 (1 bit)
host channel-2 interrupt enable register (HCH2INTEN)
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transfer completed interrupt enable
bits : 0 - 0 (1 bit)
CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)
STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)
NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)
ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)
USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)
BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)
REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)
DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)
host channel-2 transfer length register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLEN : Transfer length
bits : 0 - 18 (19 bit)
PCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
host channel-3 characteristics register (HCH3CTL)
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPL : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSD : Low-speed device
bits : 17 - 17 (1 bit)
EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)
DAR : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CDIS : Channel disable
bits : 30 - 30 (1 bit)
CEN : Channel enable
bits : 31 - 31 (1 bit)
host channel-3 interrupt register (HCH3INTF)
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF : Transfer finished
bits : 0 - 0 (1 bit)
CH : Channel halted
bits : 1 - 1 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
USBER : USB bus error
bits : 7 - 7 (1 bit)
BBER : Babble error
bits : 8 - 8 (1 bit)
REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)
DTER : Data toggle error
bits : 10 - 10 (1 bit)
host channel-3 interrupt enable register (HCH3INTEN)
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transfer completed interrupt enable
bits : 0 - 0 (1 bit)
CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)
STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)
NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)
ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)
USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)
BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)
REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)
DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)
host channel-3 transfer length register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLEN : Transfer length
bits : 0 - 18 (19 bit)
PCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
host all channels interrupt mask register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CINTEN : Channel interrupt enable
bits : 0 - 7 (8 bit)
host channel-4 characteristics register (HCH4CTL)
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPL : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSD : Low-speed device
bits : 17 - 17 (1 bit)
EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)
DAR : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CDIS : Channel disable
bits : 30 - 30 (1 bit)
CEN : Channel enable
bits : 31 - 31 (1 bit)
host channel-4 interrupt register (HCH4INTF)
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF : Transfer finished
bits : 0 - 0 (1 bit)
CH : Channel halted
bits : 1 - 1 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
USBER : USB bus error
bits : 7 - 7 (1 bit)
BBER : Babble error
bits : 8 - 8 (1 bit)
REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)
DTER : Data toggle error
bits : 10 - 10 (1 bit)
host channel-4 interrupt enable register (HCH4INTEN)
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transfer completed interrupt enable
bits : 0 - 0 (1 bit)
CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)
STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)
NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)
ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)
USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)
BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)
REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)
DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)
host channel-4 transfer length register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLEN : Transfer length
bits : 0 - 18 (19 bit)
PCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
host channel-5 characteristics register (HCH5CTL)
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPL : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSD : Low-speed device
bits : 17 - 17 (1 bit)
EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)
DAR : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CDIS : Channel disable
bits : 30 - 30 (1 bit)
CEN : Channel enable
bits : 31 - 31 (1 bit)
host channel-5 interrupt register (HCH5INTF)
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF : Transfer finished
bits : 0 - 0 (1 bit)
CH : Channel halted
bits : 1 - 1 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
USBER : USB bus error
bits : 7 - 7 (1 bit)
BBER : Babble error
bits : 8 - 8 (1 bit)
REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)
DTER : Data toggle error
bits : 10 - 10 (1 bit)
host channel-5 interrupt enable register (HCH5INTEN)
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transfer completed interrupt enable
bits : 0 - 0 (1 bit)
CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)
STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)
NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)
ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)
USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)
BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)
REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)
DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)
host channel-5 transfer length register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLEN : Transfer length
bits : 0 - 18 (19 bit)
PCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
host channel-6 characteristics register (HCH6CTL)
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPL : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSD : Low-speed device
bits : 17 - 17 (1 bit)
EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)
DAR : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CDIS : Channel disable
bits : 30 - 30 (1 bit)
CEN : Channel enable
bits : 31 - 31 (1 bit)
host channel-6 interrupt register (HCH6INTF)
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF : Transfer finished
bits : 0 - 0 (1 bit)
CH : Channel halted
bits : 1 - 1 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
USBER : USB bus error
bits : 7 - 7 (1 bit)
BBER : Babble error
bits : 8 - 8 (1 bit)
REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)
DTER : Data toggle error
bits : 10 - 10 (1 bit)
host channel-6 interrupt enable register (HCH6INTEN)
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transfer completed interrupt enable
bits : 0 - 0 (1 bit)
CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)
STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)
NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)
ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)
USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)
BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)
REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)
DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)
host channel-6 transfer length register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLEN : Transfer length
bits : 0 - 18 (19 bit)
PCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
host channel-7 characteristics register (HCH7CTL)
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPL : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSD : Low-speed device
bits : 17 - 17 (1 bit)
EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)
DAR : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CDIS : Channel disable
bits : 30 - 30 (1 bit)
CEN : Channel enable
bits : 31 - 31 (1 bit)
host channel-7 interrupt register (HCH7INTF)
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF : Transfer finished
bits : 0 - 0 (1 bit)
CH : Channel halted
bits : 1 - 1 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
USBER : USB bus error
bits : 7 - 7 (1 bit)
BBER : Babble error
bits : 8 - 8 (1 bit)
REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)
DTER : Data toggle error
bits : 10 - 10 (1 bit)
host channel-7 interrupt enable register (HCH7INTEN)
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transfer completed interrupt enable
bits : 0 - 0 (1 bit)
CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)
STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)
NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)
ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)
USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)
BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)
REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)
DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)
host channel-7 transfer length register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLEN : Transfer length
bits : 0 - 18 (19 bit)
PCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
Host frame interval register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRI : Frame interval
bits : 0 - 15 (16 bit)
Host port control and status register (USBFS_HPCS)
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCST : Port connect status
bits : 0 - 0 (1 bit)
access : read-only
PCD : Port connect detected
bits : 1 - 1 (1 bit)
access : read-write
PE : Port enable
bits : 2 - 2 (1 bit)
access : read-write
PEDC : Port enable/disable change
bits : 3 - 3 (1 bit)
access : read-write
PREM : Port resume
bits : 6 - 6 (1 bit)
access : read-write
PSP : Port suspend
bits : 7 - 7 (1 bit)
access : read-write
PRST : Port reset
bits : 8 - 8 (1 bit)
access : read-write
PLST : Port line status
bits : 10 - 11 (2 bit)
access : read-only
PP : Port power
bits : 12 - 12 (1 bit)
access : read-write
PS : Port speed
bits : 17 - 18 (2 bit)
access : read-only
OTG_FS host frame number/frame time remaining register (HFINFR)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRNUM : Frame number
bits : 0 - 15 (16 bit)
FRT : Frame remaining time
bits : 16 - 31 (16 bit)
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