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ADC_Common

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :

Registers

SSTAT

SYNCCTL

SYNCDATA


SSTAT

summary status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SSTAT SSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDE0 EOC0 EOIC0 STIC0 STRC0 ROVF0 WDE1 EOC1 EOIC1 STIC1 STRC1 ROVF1 WDE2 EOC2 EOIC2 STIC2 STRC2 ROVF2

WDE0 : This bit equals to the WDE bit of ADC0
bits : 0 - 0 (1 bit)

EOC0 : This bit equals to the EOC bit of ADC0
bits : 1 - 1 (1 bit)

EOIC0 : This bit equals to the EOIC bit of ADC0
bits : 2 - 2 (1 bit)

STIC0 : This bit equals to the STIC bit of ADC0
bits : 3 - 3 (1 bit)

STRC0 : This bit equals to the STRC bit of ADC0
bits : 4 - 4 (1 bit)

ROVF0 : This bit equals to the ROVF bit of ADC0
bits : 5 - 5 (1 bit)

WDE1 : This bit equals to the WDE bit of ADC1
bits : 8 - 8 (1 bit)

EOC1 : This bit equals to the EOC bit of ADC1
bits : 9 - 9 (1 bit)

EOIC1 : This bit equals to the EOIC bit of ADC1
bits : 10 - 10 (1 bit)

STIC1 : This bit equals to the STIC bit of ADC1
bits : 11 - 11 (1 bit)

STRC1 : This bit equals to the STRC bit of ADC1
bits : 12 - 12 (1 bit)

ROVF1 : This bit equals to the ROVF bit of ADC1
bits : 13 - 13 (1 bit)

WDE2 : This bit equals to the WDE bit of ADC2
bits : 16 - 16 (1 bit)

EOC2 : This bit equals to the EOC bit of ADC2
bits : 17 - 17 (1 bit)

EOIC2 : This bit equals to the EOIC bit of ADC2
bits : 18 - 18 (1 bit)

STIC2 : This bit equals to the STIC bit of ADC2
bits : 19 - 19 (1 bit)

STRC2 : This bit equals to the STRC bit of ADC2
bits : 20 - 20 (1 bit)

ROVF2 : This bit equals to the ROVF bit of ADC2
bits : 21 - 21 (1 bit)


SYNCCTL

sync control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNCCTL SYNCCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNCM SYNCDLY SYNCDDM SYNCDMA ADCCK VBATEN TSVREN

SYNCM : ADC sync mode
bits : 0 - 4 (5 bit)

SYNCDLY : ADC sync delay
bits : 8 - 11 (4 bit)

SYNCDDM : ADC sync DMA disable mode
bits : 13 - 13 (1 bit)

SYNCDMA : ADC sync DMA mode selection
bits : 14 - 15 (2 bit)

ADCCK : ADC clock
bits : 16 - 18 (3 bit)

VBATEN : Channel 18 (1/4 voltate of external battery) enable of ADC0
bits : 22 - 22 (1 bit)

TSVREN : Channel 16 (temperature sensor) and 17 (internal reference voltage) enable of ADC0
bits : 23 - 23 (1 bit)


SYNCDATA

Sync regular data register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCDATA SYNCDATA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNCDATA1 SYNCDATA2

SYNCDATA1 : Regular data1 in ADC sync mode
bits : 0 - 15 (16 bit)

SYNCDATA2 : Regular data2 in ADC sync mode
bits : 16 - 31 (16 bit)



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