\n

DBG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

ID

CTL0

CTL1

CTL2


ID

ID code register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ID ID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_CODE

ID_CODE : DBG ID code register
bits : 0 - 31 (32 bit)


CTL0

Control register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL0 CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLP_HOLD DSLP_HOLD STB_HOLD TRACE_IOEN TRACE_MODE

SLP_HOLD : Sleep mode hold register
bits : 0 - 0 (1 bit)

DSLP_HOLD : Deep-sleep mode hold register
bits : 1 - 1 (1 bit)

STB_HOLD : Standby mode hold register
bits : 2 - 2 (1 bit)

TRACE_IOEN : Trace pin allocation enable
bits : 5 - 5 (1 bit)

TRACE_MODE : Trace pin allocation mode
bits : 6 - 7 (2 bit)


CTL1

Control register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL1 CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER1_HOLD TIMER2_HOLD TIMER3_HOLD TIMER4_HOLD TIMER5_HOLD TIMER6_HOLD TIMER11_HOLD TIMER12_HOLD TIMER13_HOLD RTC_HOLD WWDGT_HOLD FWDGT_HOLD I2C0_HOLD I2C1_HOLD I2C2_HOLD CAN0_HOLD CAN1_HOLD

TIMER1_HOLD : TIMER 1 hold register
bits : 0 - 0 (1 bit)

TIMER2_HOLD : TIMER 2 hold register
bits : 1 - 1 (1 bit)

TIMER3_HOLD : TIMER 3 hold register
bits : 2 - 2 (1 bit)

TIMER4_HOLD : TIMER 4 hold register
bits : 3 - 3 (1 bit)

TIMER5_HOLD : TIMER 5 hold register
bits : 4 - 4 (1 bit)

TIMER6_HOLD : TIMER 6 hold register
bits : 5 - 5 (1 bit)

TIMER11_HOLD : TIMER 11 hold register
bits : 6 - 6 (1 bit)

TIMER12_HOLD : TIMER 12 hold register
bits : 7 - 7 (1 bit)

TIMER13_HOLD : TIMER 13 hold register
bits : 8 - 8 (1 bit)

RTC_HOLD : RTC hold register
bits : 10 - 10 (1 bit)

WWDGT_HOLD : WWDGT hold register
bits : 11 - 11 (1 bit)

FWDGT_HOLD : FWDGT hold register
bits : 12 - 12 (1 bit)

I2C0_HOLD : I2C0 hold register
bits : 21 - 21 (1 bit)

I2C1_HOLD : I2C1 hold register
bits : 22 - 22 (1 bit)

I2C2_HOLD : I2C2 hold register
bits : 23 - 23 (1 bit)

CAN0_HOLD : CAN0 hold register
bits : 25 - 25 (1 bit)

CAN1_HOLD : CAN1 hold register
bits : 26 - 26 (1 bit)


CTL2

Control register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL2 CTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER0_HOLD TIMER7_HOLD TIMER8_HOLD TIMER9_HOLD TIMER10_HOLD

TIMER0_HOLD : TIMER 0 hold register
bits : 0 - 0 (1 bit)

TIMER7_HOLD : TIMER 7 hold register
bits : 1 - 1 (1 bit)

TIMER8_HOLD : TIMER 8 hold register
bits : 16 - 16 (1 bit)

TIMER9_HOLD : TIMER 9 hold register
bits : 17 - 17 (1 bit)

TIMER10_HOLD : TIMER 10 hold register
bits : 18 - 18 (1 bit)



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