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DMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

INTF0

CH0CTL

CH0CNT

CH0PADDR

CH0M0ADDR

CH0M1ADDR

CH0FCTL

CH1CTL

CH1CNT

CH1PADDR

CH1M0ADDR

CH1M1ADDR

CH1FCTL

INTF1

CH2CTL

CH2CNT

CH2PADDR

CH2M0ADDR

CH2M1ADDR

CH2FCTL

CH3CTL

CH3CNT

CH3PADDR

CH3M0ADDR

CH3M1ADDR

CH3FCTL

CH4CTL

CH4CNT

CH4PADDR

CH4M0ADDR

INTC0

CH4M1ADDR

CH4FCTL

CH5CTL

CH5CNT

CH5PADDR

CH5M0ADDR

CH5M1ADDR

CH5FCTL

CH6CTL

CH6CNT

CH6PADDR

CH6M0ADDR

CH6M1ADDR

CH6FCTL

CH7CTL

CH7CNT

INTC1

CH7PADDR

CH7M0ADDR

CH7M1ADDR

CH7FCTL


INTF0

Interrupt flag register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTF0 INTF0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEEIF0 SDEIF0 TAEIF0 HTFIF0 FTFIF0 FEEIF1 SDEIF1 TAEIF1 HTFIF1 FTFIF1 FEEIF2 SDEIF2 TAEIF2 HTFIF2 FTFIF2 FEEIF3 SDEIF3 TAEIF3 HTFIF3 FTFIF3

FEEIF0 : FIFO error and exception of channel 0
bits : 0 - 0 (1 bit)

SDEIF0 : Single data mode exception of channel 0
bits : 2 - 2 (1 bit)

TAEIF0 : Transfer access error flag of channel 0
bits : 3 - 3 (1 bit)

HTFIF0 : Half transfer finish flag of channel 0
bits : 4 - 4 (1 bit)

FTFIF0 : Full Transfer finish flag of channel 0
bits : 5 - 5 (1 bit)

FEEIF1 : FIFO error and exception of channel 1
bits : 6 - 6 (1 bit)

SDEIF1 : Single data mode exception of channel 1
bits : 8 - 8 (1 bit)

TAEIF1 : Transfer access error flag of channel 1
bits : 9 - 9 (1 bit)

HTFIF1 : Half transfer finish flag of channel 1
bits : 10 - 10 (1 bit)

FTFIF1 : Full Transfer finish flag of channel 1
bits : 11 - 11 (1 bit)

FEEIF2 : FIFO error and exception of channel 2
bits : 16 - 16 (1 bit)

SDEIF2 : Single data mode exception of channel 2
bits : 18 - 18 (1 bit)

TAEIF2 : Transfer access error flag of channel 2
bits : 19 - 19 (1 bit)

HTFIF2 : Half transfer finish flag of channel 2
bits : 20 - 20 (1 bit)

FTFIF2 : Full Transfer finish flag of channel 2
bits : 21 - 21 (1 bit)

FEEIF3 : FIFO error and exception of channel 3
bits : 22 - 22 (1 bit)

SDEIF3 : Single data mode exception of channel 3
bits : 24 - 24 (1 bit)

TAEIF3 : Transfer access error flag of channel 3
bits : 25 - 25 (1 bit)

HTFIF3 : Half transfer finish flag of channel 3
bits : 26 - 26 (1 bit)

FTFIF3 : Full Transfer finish flag of channel 3
bits : 27 - 27 (1 bit)


CH0CTL

Channel 0 control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0CTL CH0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN SDEIE TAEIE HTFIE FTFIE TFCS TM CMEN PNAGA MNAGA PWIDTH MWIDTH PAIF PRIO SBMEN MBS PBURST MBURST PERIEN

CHEN : Channel enable
bits : 0 - 0 (1 bit)

SDEIE : Enable bit for single data mode exception interrupt
bits : 1 - 1 (1 bit)

TAEIE : Enable bit for tranfer access error interrupt
bits : 2 - 2 (1 bit)

HTFIE : Enable bit for half transfer finish interrupt
bits : 3 - 3 (1 bit)

FTFIE : Enable bit for full transfer finish interrupt
bits : 4 - 4 (1 bit)

TFCS : Transfer flow controller select
bits : 5 - 5 (1 bit)

TM : Transfer mode
bits : 6 - 7 (2 bit)

CMEN : Circulation mode enable
bits : 8 - 8 (1 bit)

PNAGA : Next address generation algorithm of peripheral
bits : 9 - 9 (1 bit)

MNAGA : Next address generation algorithm of memory
bits : 10 - 10 (1 bit)

PWIDTH : Transfer width of peripheral
bits : 11 - 12 (2 bit)

MWIDTH : Transfer width of memory
bits : 13 - 14 (2 bit)

PAIF : Peripheral address increment fixed
bits : 15 - 15 (1 bit)

PRIO : Priority level
bits : 16 - 17 (2 bit)

SBMEN : Switch-buffer mode enable
bits : 18 - 18 (1 bit)

MBS : Memory buffer select
bits : 19 - 19 (1 bit)

PBURST : Transfer burst type of peripheral
bits : 21 - 22 (2 bit)

MBURST : Transfer burst type of memory
bits : 23 - 24 (2 bit)

PERIEN : Peripheral enable
bits : 25 - 27 (3 bit)


CH0CNT

Channel 0 counter register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0CNT CH0CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Transfer counter
bits : 0 - 15 (16 bit)


CH0PADDR

Channel 0 peripheral base address register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0PADDR CH0PADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR

PADDR : Peripheral base address
bits : 0 - 31 (32 bit)


CH0M0ADDR

Channel 0 memory 0 base address register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0M0ADDR CH0M0ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0ADDR

M0ADDR : Memory 0 base address
bits : 0 - 31 (32 bit)


CH0M1ADDR

Channel 0 memory 1 base address register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0M1ADDR CH0M1ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1ADDR

M1ADDR : Memory 1 base address
bits : 0 - 31 (32 bit)


CH0FCTL

Channel 0 FIFO control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0FCTL CH0FCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCCV MDMEN FCNT FEEIE

FCCV : FIFO counter critical value
bits : 0 - 1 (2 bit)

MDMEN : Multi-data mode enable
bits : 2 - 2 (1 bit)

FCNT : FIFO counter
bits : 3 - 5 (3 bit)

FEEIE : Enable bit for FIFO error and exception interrupt
bits : 7 - 7 (1 bit)


CH1CTL

Channel 1 control register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CTL CH1CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN SDEIE TAEIE HTFIE FTFIE TFCS TM CMEN PNAGA MNAGA PWIDTH MWIDTH PAIF PRIO SBMEN MBS PBURST MBURST PERIEN

CHEN : Channel enable
bits : 0 - 0 (1 bit)

SDEIE : Enable bit for single data mode exception interrupt
bits : 1 - 1 (1 bit)

TAEIE : Enable bit for tranfer access error interrupt
bits : 2 - 2 (1 bit)

HTFIE : Enable bit for half transfer finish interrupt
bits : 3 - 3 (1 bit)

FTFIE : Enable bit for full transfer finish interrupt
bits : 4 - 4 (1 bit)

TFCS : Transfer flow controller select
bits : 5 - 5 (1 bit)

TM : Transfer mode
bits : 6 - 7 (2 bit)

CMEN : Circulation mode enable
bits : 8 - 8 (1 bit)

PNAGA : Next address generation algorithm of peripheral
bits : 9 - 9 (1 bit)

MNAGA : Next address generation algorithm of memory
bits : 10 - 10 (1 bit)

PWIDTH : Transfer width of peripheral
bits : 11 - 12 (2 bit)

MWIDTH : Transfer width of memory
bits : 13 - 14 (2 bit)

PAIF : Peripheral address increment fixed
bits : 15 - 15 (1 bit)

PRIO : Priority level
bits : 16 - 17 (2 bit)

SBMEN : Switch-buffer mode enable
bits : 18 - 18 (1 bit)

MBS : Memory buffer select
bits : 19 - 19 (1 bit)

PBURST : Transfer burst type of peripheral
bits : 21 - 22 (2 bit)

MBURST : Transfer burst type of memory
bits : 23 - 24 (2 bit)

PERIEN : Peripheral enable
bits : 25 - 27 (3 bit)


CH1CNT

Channel 1 counter register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CNT CH1CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Transfer counter
bits : 0 - 15 (16 bit)


CH1PADDR

Channel 1 peripheral base address register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1PADDR CH1PADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR

PADDR : Peripheral base address
bits : 0 - 31 (32 bit)


CH1M0ADDR

Channel 1 memory 0 base address register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1M0ADDR CH1M0ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0ADDR

M0ADDR : Memory 0 base address
bits : 0 - 31 (32 bit)


CH1M1ADDR

Channel 1 memory 1 base address register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1M1ADDR CH1M1ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1ADDR

M1ADDR : Memory 1 base address
bits : 0 - 31 (32 bit)


CH1FCTL

Channel 1 FIFO control register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1FCTL CH1FCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCCV MDMEN FCNT FEEIE

FCCV : FIFO counter critical value
bits : 0 - 1 (2 bit)

MDMEN : Multi-data mode enable
bits : 2 - 2 (1 bit)

FCNT : FIFO counter
bits : 3 - 5 (3 bit)

FEEIE : Enable bit for FIFO error and exception interrupt
bits : 7 - 7 (1 bit)


INTF1

Interrupt flag register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTF1 INTF1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEEIF4 SDEIF4 TAEIF4 HTFIF4 FTFIF4 FEEIF5 SDEIF5 TAEIF5 HTFIF5 FTFIF5 FEEIF6 SDEIF6 TAEIF6 HTFIF6 FTFIF6 FEEIF7 SDEIF7 TAEIF7 HTFIF7 FTFIF7

FEEIF4 : FIFO error and exception of channel 4
bits : 0 - 0 (1 bit)

SDEIF4 : Single data mode exception of channel 4
bits : 2 - 2 (1 bit)

TAEIF4 : Transfer access error flag of channel 4
bits : 3 - 3 (1 bit)

HTFIF4 : Half transfer finish flag of channel 4
bits : 4 - 4 (1 bit)

FTFIF4 : Full Transfer finish flag of channel 4
bits : 5 - 5 (1 bit)

FEEIF5 : FIFO error and exception of channel 5
bits : 6 - 6 (1 bit)

SDEIF5 : Single data mode exception of channel 5
bits : 8 - 8 (1 bit)

TAEIF5 : Transfer access error flag of channel 5
bits : 9 - 9 (1 bit)

HTFIF5 : Half transfer finish flag of channel 5
bits : 10 - 10 (1 bit)

FTFIF5 : Full Transfer finish flag of channel 5
bits : 11 - 11 (1 bit)

FEEIF6 : FIFO error and exception of channel 6
bits : 16 - 16 (1 bit)

SDEIF6 : Single data mode exception of channel 6
bits : 18 - 18 (1 bit)

TAEIF6 : Transfer access error flag of channel 6
bits : 19 - 19 (1 bit)

HTFIF6 : Half transfer finish flag of channel 6
bits : 20 - 20 (1 bit)

FTFIF6 : Full Transfer finish flag of channel 6
bits : 21 - 21 (1 bit)

FEEIF7 : FIFO error and exception of channel 7
bits : 22 - 22 (1 bit)

SDEIF7 : Single data mode exception of channel 7
bits : 24 - 24 (1 bit)

TAEIF7 : Transfer access error flag of channel 7
bits : 25 - 25 (1 bit)

HTFIF7 : Half transfer finish flag of channel 7
bits : 26 - 26 (1 bit)

FTFIF7 : Full Transfer finish flag of channel 7
bits : 27 - 27 (1 bit)


CH2CTL

Channel 2 control register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2CTL CH2CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN SDEIE TAEIE HTFIE FTFIE TFCS TM CMEN PNAGA MNAGA PWIDTH MWIDTH PAIF PRIO SBMEN MBS PBURST MBURST PERIEN

CHEN : Channel enable
bits : 0 - 0 (1 bit)

SDEIE : Enable bit for single data mode exception interrupt
bits : 1 - 1 (1 bit)

TAEIE : Enable bit for tranfer access error interrupt
bits : 2 - 2 (1 bit)

HTFIE : Enable bit for half transfer finish interrupt
bits : 3 - 3 (1 bit)

FTFIE : Enable bit for full transfer finish interrupt
bits : 4 - 4 (1 bit)

TFCS : Transfer flow controller select
bits : 5 - 5 (1 bit)

TM : Transfer mode
bits : 6 - 7 (2 bit)

CMEN : Circulation mode enable
bits : 8 - 8 (1 bit)

PNAGA : Next address generation algorithm of peripheral
bits : 9 - 9 (1 bit)

MNAGA : Next address generation algorithm of memory
bits : 10 - 10 (1 bit)

PWIDTH : Transfer width of peripheral
bits : 11 - 12 (2 bit)

MWIDTH : Transfer width of memory
bits : 13 - 14 (2 bit)

PAIF : Peripheral address increment fixed
bits : 15 - 15 (1 bit)

PRIO : Priority level
bits : 16 - 17 (2 bit)

SBMEN : Switch-buffer mode enable
bits : 18 - 18 (1 bit)

MBS : Memory buffer select
bits : 19 - 19 (1 bit)

PBURST : Transfer burst type of peripheral
bits : 21 - 22 (2 bit)

MBURST : Transfer burst type of memory
bits : 23 - 24 (2 bit)

PERIEN : Peripheral enable
bits : 25 - 27 (3 bit)


CH2CNT

Channel 2 counter register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2CNT CH2CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Transfer counter
bits : 0 - 15 (16 bit)


CH2PADDR

Channel 2 peripheral base address register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2PADDR CH2PADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR

PADDR : Peripheral base address
bits : 0 - 31 (32 bit)


CH2M0ADDR

Channel 2 memory 0 base address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2M0ADDR CH2M0ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0ADDR

M0ADDR : Memory 0 base address
bits : 0 - 31 (32 bit)


CH2M1ADDR

Channel 2 memory 1 base address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2M1ADDR CH2M1ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1ADDR

M1ADDR : Memory 1 base address
bits : 0 - 31 (32 bit)


CH2FCTL

Channel 2 FIFO control register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2FCTL CH2FCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCCV MDMEN FCNT FEEIE

FCCV : FIFO counter critical value
bits : 0 - 1 (2 bit)

MDMEN : Multi-data mode enable
bits : 2 - 2 (1 bit)

FCNT : FIFO counter
bits : 3 - 5 (3 bit)

FEEIE : Enable bit for FIFO error and exception interrupt
bits : 7 - 7 (1 bit)


CH3CTL

Channel 3 control register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3CTL CH3CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN SDEIE TAEIE HTFIE FTFIE TFCS TM CMEN PNAGA MNAGA PWIDTH MWIDTH PAIF PRIO SBMEN MBS PBURST MBURST PERIEN

CHEN : Channel enable
bits : 0 - 0 (1 bit)

SDEIE : Enable bit for single data mode exception interrupt
bits : 1 - 1 (1 bit)

TAEIE : Enable bit for tranfer access error interrupt
bits : 2 - 2 (1 bit)

HTFIE : Enable bit for half transfer finish interrupt
bits : 3 - 3 (1 bit)

FTFIE : Enable bit for full transfer finish interrupt
bits : 4 - 4 (1 bit)

TFCS : Transfer flow controller select
bits : 5 - 5 (1 bit)

TM : Transfer mode
bits : 6 - 7 (2 bit)

CMEN : Circulation mode enable
bits : 8 - 8 (1 bit)

PNAGA : Next address generation algorithm of peripheral
bits : 9 - 9 (1 bit)

MNAGA : Next address generation algorithm of memory
bits : 10 - 10 (1 bit)

PWIDTH : Transfer width of peripheral
bits : 11 - 12 (2 bit)

MWIDTH : Transfer width of memory
bits : 13 - 14 (2 bit)

PAIF : Peripheral address increment fixed
bits : 15 - 15 (1 bit)

PRIO : Priority level
bits : 16 - 17 (2 bit)

SBMEN : Switch-buffer mode enable
bits : 18 - 18 (1 bit)

MBS : Memory buffer select
bits : 19 - 19 (1 bit)

PBURST : Transfer burst type of peripheral
bits : 21 - 22 (2 bit)

MBURST : Transfer burst type of memory
bits : 23 - 24 (2 bit)

PERIEN : Peripheral enable
bits : 25 - 27 (3 bit)


CH3CNT

Channel 3 counter register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3CNT CH3CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Transfer counter
bits : 0 - 15 (16 bit)


CH3PADDR

Channel 3 peripheral base address register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3PADDR CH3PADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR

PADDR : Peripheral base address
bits : 0 - 31 (32 bit)


CH3M0ADDR

Channel 3 memory 0 base address register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3M0ADDR CH3M0ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0ADDR

M0ADDR : Memory 0 base address
bits : 0 - 31 (32 bit)


CH3M1ADDR

Channel 3 memory 1 base address register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3M1ADDR CH3M1ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1ADDR

M1ADDR : Memory 1 base address
bits : 0 - 31 (32 bit)


CH3FCTL

Channel 3 FIFO control register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3FCTL CH3FCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCCV MDMEN FCNT FEEIE

FCCV : FIFO counter critical value
bits : 0 - 1 (2 bit)

MDMEN : Multi-data mode enable
bits : 2 - 2 (1 bit)

FCNT : FIFO counter
bits : 3 - 5 (3 bit)

FEEIE : Enable bit for FIFO error and exception interrupt
bits : 7 - 7 (1 bit)


CH4CTL

Channel 4 control register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4CTL CH4CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN SDEIE TAEIE HTFIE FTFIE TFCS TM CMEN PNAGA MNAGA PWIDTH MWIDTH PAIF PRIO SBMEN MBS PBURST MBURST PERIEN

CHEN : Channel enable
bits : 0 - 0 (1 bit)

SDEIE : Enable bit for single data mode exception interrupt
bits : 1 - 1 (1 bit)

TAEIE : Enable bit for tranfer access error interrupt
bits : 2 - 2 (1 bit)

HTFIE : Enable bit for half transfer finish interrupt
bits : 3 - 3 (1 bit)

FTFIE : Enable bit for full transfer finish interrupt
bits : 4 - 4 (1 bit)

TFCS : Transfer flow controller select
bits : 5 - 5 (1 bit)

TM : Transfer mode
bits : 6 - 7 (2 bit)

CMEN : Circulation mode enable
bits : 8 - 8 (1 bit)

PNAGA : Next address generation algorithm of peripheral
bits : 9 - 9 (1 bit)

MNAGA : Next address generation algorithm of memory
bits : 10 - 10 (1 bit)

PWIDTH : Transfer width of peripheral
bits : 11 - 12 (2 bit)

MWIDTH : Transfer width of memory
bits : 13 - 14 (2 bit)

PAIF : Peripheral address increment fixed
bits : 15 - 15 (1 bit)

PRIO : Priority level
bits : 16 - 17 (2 bit)

SBMEN : Switch-buffer mode enable
bits : 18 - 18 (1 bit)

MBS : Memory buffer select
bits : 19 - 19 (1 bit)

PBURST : Transfer burst type of peripheral
bits : 21 - 22 (2 bit)

MBURST : Transfer burst type of memory
bits : 23 - 24 (2 bit)

PERIEN : Peripheral enable
bits : 25 - 27 (3 bit)


CH4CNT

Channel 4 counter register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4CNT CH4CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Transfer counter
bits : 0 - 15 (16 bit)


CH4PADDR

Channel 4 peripheral base address register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4PADDR CH4PADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR

PADDR : Peripheral base address
bits : 0 - 31 (32 bit)


CH4M0ADDR

Channel 4 memory 0 base address register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4M0ADDR CH4M0ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0ADDR

M0ADDR : Memory 0 base address
bits : 0 - 31 (32 bit)


INTC0

Interrupt flag clear register 0
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INTC0 INTC0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEEIFC0 SDEIFC0 TAEIFC0 HTFIFC0 FTFIFC0 FEEIFC1 SDEIFC1 TAEIFC1 HTFIFC1 FTFIFC1 FEEIFC2 SDEIFC2 TAEIFC2 HTFIFC2 FTFIFC2 FEEIFC3 SDEIFC3 TAEIFC3 HTFIFC3 FTFIFC3

FEEIFC0 : Clear bit for FIFO error and exception of channel 0
bits : 0 - 0 (1 bit)

SDEIFC0 : Clear bit for single data mode exception of channel 0
bits : 2 - 2 (1 bit)

TAEIFC0 : Clear bit for transfer access error flag of channel 0
bits : 3 - 3 (1 bit)

HTFIFC0 : Clear bit for half transfer finish flag of channel 0
bits : 4 - 4 (1 bit)

FTFIFC0 : Clear bit for Full transfer finish flag of channel 0
bits : 5 - 5 (1 bit)

FEEIFC1 : Clear bit for FIFO error and exception of channel 1
bits : 6 - 6 (1 bit)

SDEIFC1 : Clear bit for single data mode exception of channel 1
bits : 8 - 8 (1 bit)

TAEIFC1 : Clear bit for transfer access error flag of channel 1
bits : 9 - 9 (1 bit)

HTFIFC1 : Clear bit for half transfer finish flag of channel 1
bits : 10 - 10 (1 bit)

FTFIFC1 : Clear bit for Full transfer finish flag of channel 1
bits : 11 - 11 (1 bit)

FEEIFC2 : Clear bit for FIFO error and exception of channel 2
bits : 16 - 16 (1 bit)

SDEIFC2 : Clear bit for single data mode exception of channel 2
bits : 18 - 18 (1 bit)

TAEIFC2 : Clear bit for transfer access error flag of channel 2
bits : 19 - 19 (1 bit)

HTFIFC2 : Clear bit for half transfer finish flag of channel 2
bits : 20 - 20 (1 bit)

FTFIFC2 : Clear bit for Full transfer finish flag of channel 2
bits : 21 - 21 (1 bit)

FEEIFC3 : Clear bit for FIFO error and exception of channel 3
bits : 22 - 22 (1 bit)

SDEIFC3 : Clear bit for single data mode exception of channel 3
bits : 24 - 24 (1 bit)

TAEIFC3 : Clear bit for transfer access error flag of channel 3
bits : 25 - 25 (1 bit)

HTFIFC3 : Clear bit for half transfer finish flag of channel 3
bits : 26 - 26 (1 bit)

FTFIFC3 : Clear bit for Full transfer finish flag of channel 3
bits : 27 - 27 (1 bit)


CH4M1ADDR

Channel 4 memory 1 base address register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4M1ADDR CH4M1ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1ADDR

M1ADDR : Memory 1 base address
bits : 0 - 31 (32 bit)


CH4FCTL

Channel 4 FIFO control register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4FCTL CH4FCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCCV MDMEN FCNT FEEIE

FCCV : FIFO counter critical value
bits : 0 - 1 (2 bit)

MDMEN : Multi-data mode enable
bits : 2 - 2 (1 bit)

FCNT : FIFO counter
bits : 3 - 5 (3 bit)

FEEIE : Enable bit for FIFO error and exception interrupt
bits : 7 - 7 (1 bit)


CH5CTL

Channel 5 control register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5CTL CH5CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN SDEIE TAEIE HTFIE FTFIE TFCS TM CMEN PNAGA MNAGA PWIDTH MWIDTH PAIF PRIO SBMEN MBS PBURST MBURST PERIEN

CHEN : Channel enable
bits : 0 - 0 (1 bit)

SDEIE : Enable bit for single data mode exception interrupt
bits : 1 - 1 (1 bit)

TAEIE : Enable bit for tranfer access error interrupt
bits : 2 - 2 (1 bit)

HTFIE : Enable bit for half transfer finish interrupt
bits : 3 - 3 (1 bit)

FTFIE : Enable bit for full transfer finish interrupt
bits : 4 - 4 (1 bit)

TFCS : Transfer flow controller select
bits : 5 - 5 (1 bit)

TM : Transfer mode
bits : 6 - 7 (2 bit)

CMEN : Circulation mode enable
bits : 8 - 8 (1 bit)

PNAGA : Next address generation algorithm of peripheral
bits : 9 - 9 (1 bit)

MNAGA : Next address generation algorithm of memory
bits : 10 - 10 (1 bit)

PWIDTH : Transfer width of peripheral
bits : 11 - 12 (2 bit)

MWIDTH : Transfer width of memory
bits : 13 - 14 (2 bit)

PAIF : Peripheral address increment fixed
bits : 15 - 15 (1 bit)

PRIO : Priority level
bits : 16 - 17 (2 bit)

SBMEN : Switch-buffer mode enable
bits : 18 - 18 (1 bit)

MBS : Memory buffer select
bits : 19 - 19 (1 bit)

PBURST : Transfer burst type of peripheral
bits : 21 - 22 (2 bit)

MBURST : Transfer burst type of memory
bits : 23 - 24 (2 bit)

PERIEN : Peripheral enable
bits : 25 - 27 (3 bit)


CH5CNT

Channel 5 counter register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5CNT CH5CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Transfer counter
bits : 0 - 15 (16 bit)


CH5PADDR

Channel 5 peripheral base address register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5PADDR CH5PADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR

PADDR : Peripheral base address
bits : 0 - 31 (32 bit)


CH5M0ADDR

Channel 5 memory 0 base address register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5M0ADDR CH5M0ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0ADDR

M0ADDR : Memory 0 base address
bits : 0 - 31 (32 bit)


CH5M1ADDR

Channel 5 memory 1 base address register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5M1ADDR CH5M1ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1ADDR

M1ADDR : Memory 1 base address
bits : 0 - 31 (32 bit)


CH5FCTL

Channel 5 FIFO control register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5FCTL CH5FCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCCV MDMEN FCNT FEEIE

FCCV : FIFO counter critical value
bits : 0 - 1 (2 bit)

MDMEN : Multi-data mode enable
bits : 2 - 2 (1 bit)

FCNT : FIFO counter
bits : 3 - 5 (3 bit)

FEEIE : Enable bit for FIFO error and exception interrupt
bits : 7 - 7 (1 bit)


CH6CTL

Channel 6 control register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6CTL CH6CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN SDEIE TAEIE HTFIE FTFIE TFCS TM CMEN PNAGA MNAGA PWIDTH MWIDTH PAIF PRIO SBMEN MBS PBURST MBURST PERIEN

CHEN : Channel enable
bits : 0 - 0 (1 bit)

SDEIE : Enable bit for single data mode exception interrupt
bits : 1 - 1 (1 bit)

TAEIE : Enable bit for tranfer access error interrupt
bits : 2 - 2 (1 bit)

HTFIE : Enable bit for half transfer finish interrupt
bits : 3 - 3 (1 bit)

FTFIE : Enable bit for full transfer finish interrupt
bits : 4 - 4 (1 bit)

TFCS : Transfer flow controller select
bits : 5 - 5 (1 bit)

TM : Transfer mode
bits : 6 - 7 (2 bit)

CMEN : Circulation mode enable
bits : 8 - 8 (1 bit)

PNAGA : Next address generation algorithm of peripheral
bits : 9 - 9 (1 bit)

MNAGA : Next address generation algorithm of memory
bits : 10 - 10 (1 bit)

PWIDTH : Transfer width of peripheral
bits : 11 - 12 (2 bit)

MWIDTH : Transfer width of memory
bits : 13 - 14 (2 bit)

PAIF : Peripheral address increment fixed
bits : 15 - 15 (1 bit)

PRIO : Priority level
bits : 16 - 17 (2 bit)

SBMEN : Switch-buffer mode enable
bits : 18 - 18 (1 bit)

MBS : Memory buffer select
bits : 19 - 19 (1 bit)

PBURST : Transfer burst type of peripheral
bits : 21 - 22 (2 bit)

MBURST : Transfer burst type of memory
bits : 23 - 24 (2 bit)

PERIEN : Peripheral enable
bits : 25 - 27 (3 bit)


CH6CNT

Channel 6 counter register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6CNT CH6CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Transfer counter
bits : 0 - 15 (16 bit)


CH6PADDR

Channel 6 peripheral base address register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6PADDR CH6PADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR

PADDR : Peripheral base address
bits : 0 - 31 (32 bit)


CH6M0ADDR

Channel 6 memory 0 base address register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6M0ADDR CH6M0ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0ADDR

M0ADDR : Memory 0 base address
bits : 0 - 31 (32 bit)


CH6M1ADDR

Channel 6 memory 1 base address register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6M1ADDR CH6M1ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1ADDR

M1ADDR : Memory 1 base address
bits : 0 - 31 (32 bit)


CH6FCTL

Channel 6 FIFO control register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6FCTL CH6FCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCCV MDMEN FCNT FEEIE

FCCV : FIFO counter critical value
bits : 0 - 1 (2 bit)

MDMEN : Multi-data mode enable
bits : 2 - 2 (1 bit)

FCNT : FIFO counter
bits : 3 - 5 (3 bit)

FEEIE : Enable bit for FIFO error and exception interrupt
bits : 7 - 7 (1 bit)


CH7CTL

Channel 7 control register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7CTL CH7CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN SDEIE TAEIE HTFIE FTFIE TFCS TM CMEN PNAGA MNAGA PWIDTH MWIDTH PAIF PRIO SBMEN MBS PBURST MBURST PERIEN

CHEN : Channel enable
bits : 0 - 0 (1 bit)

SDEIE : Enable bit for single data mode exception interrupt
bits : 1 - 1 (1 bit)

TAEIE : Enable bit for tranfer access error interrupt
bits : 2 - 2 (1 bit)

HTFIE : Enable bit for half transfer finish interrupt
bits : 3 - 3 (1 bit)

FTFIE : Enable bit for full transfer finish interrupt
bits : 4 - 4 (1 bit)

TFCS : Transfer flow controller select
bits : 5 - 5 (1 bit)

TM : Transfer mode
bits : 6 - 7 (2 bit)

CMEN : Circulation mode enable
bits : 8 - 8 (1 bit)

PNAGA : Next address generation algorithm of peripheral
bits : 9 - 9 (1 bit)

MNAGA : Next address generation algorithm of memory
bits : 10 - 10 (1 bit)

PWIDTH : Transfer width of peripheral
bits : 11 - 12 (2 bit)

MWIDTH : Transfer width of memory
bits : 13 - 14 (2 bit)

PAIF : Peripheral address increment fixed
bits : 15 - 15 (1 bit)

PRIO : Priority level
bits : 16 - 17 (2 bit)

SBMEN : Switch-buffer mode enable
bits : 18 - 18 (1 bit)

MBS : Memory buffer select
bits : 19 - 19 (1 bit)

PBURST : Transfer burst type of peripheral
bits : 21 - 22 (2 bit)

MBURST : Transfer burst type of memory
bits : 23 - 24 (2 bit)

PERIEN : Peripheral enable
bits : 25 - 27 (3 bit)


CH7CNT

Channel 7 counter register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7CNT CH7CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Transfer counter
bits : 0 - 15 (16 bit)


INTC1

Interrupt flag clear register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INTC1 INTC1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEEIFC4 SDEIFC4 TAEIFC4 HTFIFC4 FTFIFC4 FEEIFC5 SDEIFC5 TAEIFC5 HTFIFC5 FTFIFC5 FEEIFC6 SDEIFC6 TAEIFC6 HTFIFC6 FTFIFC6 FEEIFC7 SDEIFC7 TAEIFC7 HTFIFC7 FTFIFC7

FEEIFC4 : Clear bit for FIFO error and exception of channel 4
bits : 0 - 0 (1 bit)

SDEIFC4 : Clear bit for single data mode exception of channel 4
bits : 2 - 2 (1 bit)

TAEIFC4 : Clear bit for transfer access error flag of channel 4
bits : 3 - 3 (1 bit)

HTFIFC4 : Clear bit for half transfer finish flag of channel 4
bits : 4 - 4 (1 bit)

FTFIFC4 : Clear bit for Full transfer finish flag of channel 4
bits : 5 - 5 (1 bit)

FEEIFC5 : Clear bit for FIFO error and exception of channel 5
bits : 6 - 6 (1 bit)

SDEIFC5 : Clear bit for single data mode exception of channel 5
bits : 8 - 8 (1 bit)

TAEIFC5 : Clear bit for transfer access error flag of channel 5
bits : 9 - 9 (1 bit)

HTFIFC5 : Clear bit for half transfer finish flag of channel 5
bits : 10 - 10 (1 bit)

FTFIFC5 : Clear bit for Full transfer finish flag of channel 5
bits : 11 - 11 (1 bit)

FEEIFC6 : Clear bit for FIFO error and exception of channel 6
bits : 16 - 16 (1 bit)

SDEIFC6 : Clear bit for single data mode exception of channel 6
bits : 18 - 18 (1 bit)

TAEIFC6 : Clear bit for transfer access error flag of channel 6
bits : 19 - 19 (1 bit)

HTFIFC6 : Clear bit for half transfer finish flag of channel 6
bits : 20 - 20 (1 bit)

FTFIFC6 : Clear bit for Full transfer finish flag of channel 6
bits : 21 - 21 (1 bit)

FEEIFC7 : Clear bit for FIFO error and exception of channel 7
bits : 22 - 22 (1 bit)

SDEIFC7 : Clear bit for single data mode exception of channel 7
bits : 24 - 24 (1 bit)

TAEIFC7 : Clear bit for transfer access error flag of channel 7
bits : 25 - 25 (1 bit)

HTFIFC7 : Clear bit for half transfer finish flag of channel 7
bits : 26 - 26 (1 bit)

FTFIFC7 : Clear bit for Full transfer finish flag of channel 7
bits : 27 - 27 (1 bit)


CH7PADDR

Channel 7 peripheral base address register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7PADDR CH7PADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR

PADDR : Peripheral base address
bits : 0 - 31 (32 bit)


CH7M0ADDR

Channel 7 memory 0 base address register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7M0ADDR CH7M0ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0ADDR

M0ADDR : Memory 0 base address
bits : 0 - 31 (32 bit)


CH7M1ADDR

Channel 7 memory 1 base address register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7M1ADDR CH7M1ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1ADDR

M1ADDR : Memory 1 base address
bits : 0 - 31 (32 bit)


CH7FCTL

Channel 7 FIFO control register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7FCTL CH7FCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCCV MDMEN FCNT FEEIE

FCCV : FIFO counter critical value
bits : 0 - 1 (2 bit)

MDMEN : Multi-data mode enable
bits : 2 - 2 (1 bit)

FCNT : FIFO counter
bits : 3 - 5 (3 bit)

FEEIE : Enable bit for FIFO error and exception interrupt
bits : 7 - 7 (1 bit)



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