\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Interrupt flag register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FEEIF0 : FIFO error and exception of channel 0
bits : 0 - 0 (1 bit)
SDEIF0 : Single data mode exception of channel 0
bits : 2 - 2 (1 bit)
TAEIF0 : Transfer access error flag of channel 0
bits : 3 - 3 (1 bit)
HTFIF0 : Half transfer finish flag of channel 0
bits : 4 - 4 (1 bit)
FTFIF0 : Full Transfer finish flag of channel 0
bits : 5 - 5 (1 bit)
FEEIF1 : FIFO error and exception of channel 1
bits : 6 - 6 (1 bit)
SDEIF1 : Single data mode exception of channel 1
bits : 8 - 8 (1 bit)
TAEIF1 : Transfer access error flag of channel 1
bits : 9 - 9 (1 bit)
HTFIF1 : Half transfer finish flag of channel 1
bits : 10 - 10 (1 bit)
FTFIF1 : Full Transfer finish flag of channel 1
bits : 11 - 11 (1 bit)
FEEIF2 : FIFO error and exception of channel 2
bits : 16 - 16 (1 bit)
SDEIF2 : Single data mode exception of channel 2
bits : 18 - 18 (1 bit)
TAEIF2 : Transfer access error flag of channel 2
bits : 19 - 19 (1 bit)
HTFIF2 : Half transfer finish flag of channel 2
bits : 20 - 20 (1 bit)
FTFIF2 : Full Transfer finish flag of channel 2
bits : 21 - 21 (1 bit)
FEEIF3 : FIFO error and exception of channel 3
bits : 22 - 22 (1 bit)
SDEIF3 : Single data mode exception of channel 3
bits : 24 - 24 (1 bit)
TAEIF3 : Transfer access error flag of channel 3
bits : 25 - 25 (1 bit)
HTFIF3 : Half transfer finish flag of channel 3
bits : 26 - 26 (1 bit)
FTFIF3 : Full Transfer finish flag of channel 3
bits : 27 - 27 (1 bit)
Channel 0 control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel enable
bits : 0 - 0 (1 bit)
SDEIE : Enable bit for single data mode exception interrupt
bits : 1 - 1 (1 bit)
TAEIE : Enable bit for tranfer access error interrupt
bits : 2 - 2 (1 bit)
HTFIE : Enable bit for half transfer finish interrupt
bits : 3 - 3 (1 bit)
FTFIE : Enable bit for full transfer finish interrupt
bits : 4 - 4 (1 bit)
TFCS : Transfer flow controller select
bits : 5 - 5 (1 bit)
TM : Transfer mode
bits : 6 - 7 (2 bit)
CMEN : Circulation mode enable
bits : 8 - 8 (1 bit)
PNAGA : Next address generation algorithm of peripheral
bits : 9 - 9 (1 bit)
MNAGA : Next address generation algorithm of memory
bits : 10 - 10 (1 bit)
PWIDTH : Transfer width of peripheral
bits : 11 - 12 (2 bit)
MWIDTH : Transfer width of memory
bits : 13 - 14 (2 bit)
PAIF : Peripheral address increment fixed
bits : 15 - 15 (1 bit)
PRIO : Priority level
bits : 16 - 17 (2 bit)
SBMEN : Switch-buffer mode enable
bits : 18 - 18 (1 bit)
MBS : Memory buffer select
bits : 19 - 19 (1 bit)
PBURST : Transfer burst type of peripheral
bits : 21 - 22 (2 bit)
MBURST : Transfer burst type of memory
bits : 23 - 24 (2 bit)
PERIEN : Peripheral enable
bits : 25 - 27 (3 bit)
Channel 0 counter register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Transfer counter
bits : 0 - 15 (16 bit)
Channel 0 peripheral base address register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR : Peripheral base address
bits : 0 - 31 (32 bit)
Channel 0 memory 0 base address register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0ADDR : Memory 0 base address
bits : 0 - 31 (32 bit)
Channel 0 memory 1 base address register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M1ADDR : Memory 1 base address
bits : 0 - 31 (32 bit)
Channel 0 FIFO control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCCV : FIFO counter critical value
bits : 0 - 1 (2 bit)
MDMEN : Multi-data mode enable
bits : 2 - 2 (1 bit)
FCNT : FIFO counter
bits : 3 - 5 (3 bit)
FEEIE : Enable bit for FIFO error and exception interrupt
bits : 7 - 7 (1 bit)
Channel 1 control register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel enable
bits : 0 - 0 (1 bit)
SDEIE : Enable bit for single data mode exception interrupt
bits : 1 - 1 (1 bit)
TAEIE : Enable bit for tranfer access error interrupt
bits : 2 - 2 (1 bit)
HTFIE : Enable bit for half transfer finish interrupt
bits : 3 - 3 (1 bit)
FTFIE : Enable bit for full transfer finish interrupt
bits : 4 - 4 (1 bit)
TFCS : Transfer flow controller select
bits : 5 - 5 (1 bit)
TM : Transfer mode
bits : 6 - 7 (2 bit)
CMEN : Circulation mode enable
bits : 8 - 8 (1 bit)
PNAGA : Next address generation algorithm of peripheral
bits : 9 - 9 (1 bit)
MNAGA : Next address generation algorithm of memory
bits : 10 - 10 (1 bit)
PWIDTH : Transfer width of peripheral
bits : 11 - 12 (2 bit)
MWIDTH : Transfer width of memory
bits : 13 - 14 (2 bit)
PAIF : Peripheral address increment fixed
bits : 15 - 15 (1 bit)
PRIO : Priority level
bits : 16 - 17 (2 bit)
SBMEN : Switch-buffer mode enable
bits : 18 - 18 (1 bit)
MBS : Memory buffer select
bits : 19 - 19 (1 bit)
PBURST : Transfer burst type of peripheral
bits : 21 - 22 (2 bit)
MBURST : Transfer burst type of memory
bits : 23 - 24 (2 bit)
PERIEN : Peripheral enable
bits : 25 - 27 (3 bit)
Channel 1 counter register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Transfer counter
bits : 0 - 15 (16 bit)
Channel 1 peripheral base address register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR : Peripheral base address
bits : 0 - 31 (32 bit)
Channel 1 memory 0 base address register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0ADDR : Memory 0 base address
bits : 0 - 31 (32 bit)
Channel 1 memory 1 base address register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M1ADDR : Memory 1 base address
bits : 0 - 31 (32 bit)
Channel 1 FIFO control register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCCV : FIFO counter critical value
bits : 0 - 1 (2 bit)
MDMEN : Multi-data mode enable
bits : 2 - 2 (1 bit)
FCNT : FIFO counter
bits : 3 - 5 (3 bit)
FEEIE : Enable bit for FIFO error and exception interrupt
bits : 7 - 7 (1 bit)
Interrupt flag register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FEEIF4 : FIFO error and exception of channel 4
bits : 0 - 0 (1 bit)
SDEIF4 : Single data mode exception of channel 4
bits : 2 - 2 (1 bit)
TAEIF4 : Transfer access error flag of channel 4
bits : 3 - 3 (1 bit)
HTFIF4 : Half transfer finish flag of channel 4
bits : 4 - 4 (1 bit)
FTFIF4 : Full Transfer finish flag of channel 4
bits : 5 - 5 (1 bit)
FEEIF5 : FIFO error and exception of channel 5
bits : 6 - 6 (1 bit)
SDEIF5 : Single data mode exception of channel 5
bits : 8 - 8 (1 bit)
TAEIF5 : Transfer access error flag of channel 5
bits : 9 - 9 (1 bit)
HTFIF5 : Half transfer finish flag of channel 5
bits : 10 - 10 (1 bit)
FTFIF5 : Full Transfer finish flag of channel 5
bits : 11 - 11 (1 bit)
FEEIF6 : FIFO error and exception of channel 6
bits : 16 - 16 (1 bit)
SDEIF6 : Single data mode exception of channel 6
bits : 18 - 18 (1 bit)
TAEIF6 : Transfer access error flag of channel 6
bits : 19 - 19 (1 bit)
HTFIF6 : Half transfer finish flag of channel 6
bits : 20 - 20 (1 bit)
FTFIF6 : Full Transfer finish flag of channel 6
bits : 21 - 21 (1 bit)
FEEIF7 : FIFO error and exception of channel 7
bits : 22 - 22 (1 bit)
SDEIF7 : Single data mode exception of channel 7
bits : 24 - 24 (1 bit)
TAEIF7 : Transfer access error flag of channel 7
bits : 25 - 25 (1 bit)
HTFIF7 : Half transfer finish flag of channel 7
bits : 26 - 26 (1 bit)
FTFIF7 : Full Transfer finish flag of channel 7
bits : 27 - 27 (1 bit)
Channel 2 control register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel enable
bits : 0 - 0 (1 bit)
SDEIE : Enable bit for single data mode exception interrupt
bits : 1 - 1 (1 bit)
TAEIE : Enable bit for tranfer access error interrupt
bits : 2 - 2 (1 bit)
HTFIE : Enable bit for half transfer finish interrupt
bits : 3 - 3 (1 bit)
FTFIE : Enable bit for full transfer finish interrupt
bits : 4 - 4 (1 bit)
TFCS : Transfer flow controller select
bits : 5 - 5 (1 bit)
TM : Transfer mode
bits : 6 - 7 (2 bit)
CMEN : Circulation mode enable
bits : 8 - 8 (1 bit)
PNAGA : Next address generation algorithm of peripheral
bits : 9 - 9 (1 bit)
MNAGA : Next address generation algorithm of memory
bits : 10 - 10 (1 bit)
PWIDTH : Transfer width of peripheral
bits : 11 - 12 (2 bit)
MWIDTH : Transfer width of memory
bits : 13 - 14 (2 bit)
PAIF : Peripheral address increment fixed
bits : 15 - 15 (1 bit)
PRIO : Priority level
bits : 16 - 17 (2 bit)
SBMEN : Switch-buffer mode enable
bits : 18 - 18 (1 bit)
MBS : Memory buffer select
bits : 19 - 19 (1 bit)
PBURST : Transfer burst type of peripheral
bits : 21 - 22 (2 bit)
MBURST : Transfer burst type of memory
bits : 23 - 24 (2 bit)
PERIEN : Peripheral enable
bits : 25 - 27 (3 bit)
Channel 2 counter register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Transfer counter
bits : 0 - 15 (16 bit)
Channel 2 peripheral base address register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR : Peripheral base address
bits : 0 - 31 (32 bit)
Channel 2 memory 0 base address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0ADDR : Memory 0 base address
bits : 0 - 31 (32 bit)
Channel 2 memory 1 base address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M1ADDR : Memory 1 base address
bits : 0 - 31 (32 bit)
Channel 2 FIFO control register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCCV : FIFO counter critical value
bits : 0 - 1 (2 bit)
MDMEN : Multi-data mode enable
bits : 2 - 2 (1 bit)
FCNT : FIFO counter
bits : 3 - 5 (3 bit)
FEEIE : Enable bit for FIFO error and exception interrupt
bits : 7 - 7 (1 bit)
Channel 3 control register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel enable
bits : 0 - 0 (1 bit)
SDEIE : Enable bit for single data mode exception interrupt
bits : 1 - 1 (1 bit)
TAEIE : Enable bit for tranfer access error interrupt
bits : 2 - 2 (1 bit)
HTFIE : Enable bit for half transfer finish interrupt
bits : 3 - 3 (1 bit)
FTFIE : Enable bit for full transfer finish interrupt
bits : 4 - 4 (1 bit)
TFCS : Transfer flow controller select
bits : 5 - 5 (1 bit)
TM : Transfer mode
bits : 6 - 7 (2 bit)
CMEN : Circulation mode enable
bits : 8 - 8 (1 bit)
PNAGA : Next address generation algorithm of peripheral
bits : 9 - 9 (1 bit)
MNAGA : Next address generation algorithm of memory
bits : 10 - 10 (1 bit)
PWIDTH : Transfer width of peripheral
bits : 11 - 12 (2 bit)
MWIDTH : Transfer width of memory
bits : 13 - 14 (2 bit)
PAIF : Peripheral address increment fixed
bits : 15 - 15 (1 bit)
PRIO : Priority level
bits : 16 - 17 (2 bit)
SBMEN : Switch-buffer mode enable
bits : 18 - 18 (1 bit)
MBS : Memory buffer select
bits : 19 - 19 (1 bit)
PBURST : Transfer burst type of peripheral
bits : 21 - 22 (2 bit)
MBURST : Transfer burst type of memory
bits : 23 - 24 (2 bit)
PERIEN : Peripheral enable
bits : 25 - 27 (3 bit)
Channel 3 counter register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Transfer counter
bits : 0 - 15 (16 bit)
Channel 3 peripheral base address register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR : Peripheral base address
bits : 0 - 31 (32 bit)
Channel 3 memory 0 base address register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0ADDR : Memory 0 base address
bits : 0 - 31 (32 bit)
Channel 3 memory 1 base address register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M1ADDR : Memory 1 base address
bits : 0 - 31 (32 bit)
Channel 3 FIFO control register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCCV : FIFO counter critical value
bits : 0 - 1 (2 bit)
MDMEN : Multi-data mode enable
bits : 2 - 2 (1 bit)
FCNT : FIFO counter
bits : 3 - 5 (3 bit)
FEEIE : Enable bit for FIFO error and exception interrupt
bits : 7 - 7 (1 bit)
Channel 4 control register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel enable
bits : 0 - 0 (1 bit)
SDEIE : Enable bit for single data mode exception interrupt
bits : 1 - 1 (1 bit)
TAEIE : Enable bit for tranfer access error interrupt
bits : 2 - 2 (1 bit)
HTFIE : Enable bit for half transfer finish interrupt
bits : 3 - 3 (1 bit)
FTFIE : Enable bit for full transfer finish interrupt
bits : 4 - 4 (1 bit)
TFCS : Transfer flow controller select
bits : 5 - 5 (1 bit)
TM : Transfer mode
bits : 6 - 7 (2 bit)
CMEN : Circulation mode enable
bits : 8 - 8 (1 bit)
PNAGA : Next address generation algorithm of peripheral
bits : 9 - 9 (1 bit)
MNAGA : Next address generation algorithm of memory
bits : 10 - 10 (1 bit)
PWIDTH : Transfer width of peripheral
bits : 11 - 12 (2 bit)
MWIDTH : Transfer width of memory
bits : 13 - 14 (2 bit)
PAIF : Peripheral address increment fixed
bits : 15 - 15 (1 bit)
PRIO : Priority level
bits : 16 - 17 (2 bit)
SBMEN : Switch-buffer mode enable
bits : 18 - 18 (1 bit)
MBS : Memory buffer select
bits : 19 - 19 (1 bit)
PBURST : Transfer burst type of peripheral
bits : 21 - 22 (2 bit)
MBURST : Transfer burst type of memory
bits : 23 - 24 (2 bit)
PERIEN : Peripheral enable
bits : 25 - 27 (3 bit)
Channel 4 counter register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Transfer counter
bits : 0 - 15 (16 bit)
Channel 4 peripheral base address register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR : Peripheral base address
bits : 0 - 31 (32 bit)
Channel 4 memory 0 base address register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0ADDR : Memory 0 base address
bits : 0 - 31 (32 bit)
Interrupt flag clear register 0
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FEEIFC0 : Clear bit for FIFO error and exception of channel 0
bits : 0 - 0 (1 bit)
SDEIFC0 : Clear bit for single data mode exception of channel 0
bits : 2 - 2 (1 bit)
TAEIFC0 : Clear bit for transfer access error flag of channel 0
bits : 3 - 3 (1 bit)
HTFIFC0 : Clear bit for half transfer finish flag of channel 0
bits : 4 - 4 (1 bit)
FTFIFC0 : Clear bit for Full transfer finish flag of channel 0
bits : 5 - 5 (1 bit)
FEEIFC1 : Clear bit for FIFO error and exception of channel 1
bits : 6 - 6 (1 bit)
SDEIFC1 : Clear bit for single data mode exception of channel 1
bits : 8 - 8 (1 bit)
TAEIFC1 : Clear bit for transfer access error flag of channel 1
bits : 9 - 9 (1 bit)
HTFIFC1 : Clear bit for half transfer finish flag of channel 1
bits : 10 - 10 (1 bit)
FTFIFC1 : Clear bit for Full transfer finish flag of channel 1
bits : 11 - 11 (1 bit)
FEEIFC2 : Clear bit for FIFO error and exception of channel 2
bits : 16 - 16 (1 bit)
SDEIFC2 : Clear bit for single data mode exception of channel 2
bits : 18 - 18 (1 bit)
TAEIFC2 : Clear bit for transfer access error flag of channel 2
bits : 19 - 19 (1 bit)
HTFIFC2 : Clear bit for half transfer finish flag of channel 2
bits : 20 - 20 (1 bit)
FTFIFC2 : Clear bit for Full transfer finish flag of channel 2
bits : 21 - 21 (1 bit)
FEEIFC3 : Clear bit for FIFO error and exception of channel 3
bits : 22 - 22 (1 bit)
SDEIFC3 : Clear bit for single data mode exception of channel 3
bits : 24 - 24 (1 bit)
TAEIFC3 : Clear bit for transfer access error flag of channel 3
bits : 25 - 25 (1 bit)
HTFIFC3 : Clear bit for half transfer finish flag of channel 3
bits : 26 - 26 (1 bit)
FTFIFC3 : Clear bit for Full transfer finish flag of channel 3
bits : 27 - 27 (1 bit)
Channel 4 memory 1 base address register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M1ADDR : Memory 1 base address
bits : 0 - 31 (32 bit)
Channel 4 FIFO control register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCCV : FIFO counter critical value
bits : 0 - 1 (2 bit)
MDMEN : Multi-data mode enable
bits : 2 - 2 (1 bit)
FCNT : FIFO counter
bits : 3 - 5 (3 bit)
FEEIE : Enable bit for FIFO error and exception interrupt
bits : 7 - 7 (1 bit)
Channel 5 control register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel enable
bits : 0 - 0 (1 bit)
SDEIE : Enable bit for single data mode exception interrupt
bits : 1 - 1 (1 bit)
TAEIE : Enable bit for tranfer access error interrupt
bits : 2 - 2 (1 bit)
HTFIE : Enable bit for half transfer finish interrupt
bits : 3 - 3 (1 bit)
FTFIE : Enable bit for full transfer finish interrupt
bits : 4 - 4 (1 bit)
TFCS : Transfer flow controller select
bits : 5 - 5 (1 bit)
TM : Transfer mode
bits : 6 - 7 (2 bit)
CMEN : Circulation mode enable
bits : 8 - 8 (1 bit)
PNAGA : Next address generation algorithm of peripheral
bits : 9 - 9 (1 bit)
MNAGA : Next address generation algorithm of memory
bits : 10 - 10 (1 bit)
PWIDTH : Transfer width of peripheral
bits : 11 - 12 (2 bit)
MWIDTH : Transfer width of memory
bits : 13 - 14 (2 bit)
PAIF : Peripheral address increment fixed
bits : 15 - 15 (1 bit)
PRIO : Priority level
bits : 16 - 17 (2 bit)
SBMEN : Switch-buffer mode enable
bits : 18 - 18 (1 bit)
MBS : Memory buffer select
bits : 19 - 19 (1 bit)
PBURST : Transfer burst type of peripheral
bits : 21 - 22 (2 bit)
MBURST : Transfer burst type of memory
bits : 23 - 24 (2 bit)
PERIEN : Peripheral enable
bits : 25 - 27 (3 bit)
Channel 5 counter register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Transfer counter
bits : 0 - 15 (16 bit)
Channel 5 peripheral base address register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR : Peripheral base address
bits : 0 - 31 (32 bit)
Channel 5 memory 0 base address register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0ADDR : Memory 0 base address
bits : 0 - 31 (32 bit)
Channel 5 memory 1 base address register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M1ADDR : Memory 1 base address
bits : 0 - 31 (32 bit)
Channel 5 FIFO control register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCCV : FIFO counter critical value
bits : 0 - 1 (2 bit)
MDMEN : Multi-data mode enable
bits : 2 - 2 (1 bit)
FCNT : FIFO counter
bits : 3 - 5 (3 bit)
FEEIE : Enable bit for FIFO error and exception interrupt
bits : 7 - 7 (1 bit)
Channel 6 control register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel enable
bits : 0 - 0 (1 bit)
SDEIE : Enable bit for single data mode exception interrupt
bits : 1 - 1 (1 bit)
TAEIE : Enable bit for tranfer access error interrupt
bits : 2 - 2 (1 bit)
HTFIE : Enable bit for half transfer finish interrupt
bits : 3 - 3 (1 bit)
FTFIE : Enable bit for full transfer finish interrupt
bits : 4 - 4 (1 bit)
TFCS : Transfer flow controller select
bits : 5 - 5 (1 bit)
TM : Transfer mode
bits : 6 - 7 (2 bit)
CMEN : Circulation mode enable
bits : 8 - 8 (1 bit)
PNAGA : Next address generation algorithm of peripheral
bits : 9 - 9 (1 bit)
MNAGA : Next address generation algorithm of memory
bits : 10 - 10 (1 bit)
PWIDTH : Transfer width of peripheral
bits : 11 - 12 (2 bit)
MWIDTH : Transfer width of memory
bits : 13 - 14 (2 bit)
PAIF : Peripheral address increment fixed
bits : 15 - 15 (1 bit)
PRIO : Priority level
bits : 16 - 17 (2 bit)
SBMEN : Switch-buffer mode enable
bits : 18 - 18 (1 bit)
MBS : Memory buffer select
bits : 19 - 19 (1 bit)
PBURST : Transfer burst type of peripheral
bits : 21 - 22 (2 bit)
MBURST : Transfer burst type of memory
bits : 23 - 24 (2 bit)
PERIEN : Peripheral enable
bits : 25 - 27 (3 bit)
Channel 6 counter register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Transfer counter
bits : 0 - 15 (16 bit)
Channel 6 peripheral base address register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR : Peripheral base address
bits : 0 - 31 (32 bit)
Channel 6 memory 0 base address register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0ADDR : Memory 0 base address
bits : 0 - 31 (32 bit)
Channel 6 memory 1 base address register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M1ADDR : Memory 1 base address
bits : 0 - 31 (32 bit)
Channel 6 FIFO control register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCCV : FIFO counter critical value
bits : 0 - 1 (2 bit)
MDMEN : Multi-data mode enable
bits : 2 - 2 (1 bit)
FCNT : FIFO counter
bits : 3 - 5 (3 bit)
FEEIE : Enable bit for FIFO error and exception interrupt
bits : 7 - 7 (1 bit)
Channel 7 control register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel enable
bits : 0 - 0 (1 bit)
SDEIE : Enable bit for single data mode exception interrupt
bits : 1 - 1 (1 bit)
TAEIE : Enable bit for tranfer access error interrupt
bits : 2 - 2 (1 bit)
HTFIE : Enable bit for half transfer finish interrupt
bits : 3 - 3 (1 bit)
FTFIE : Enable bit for full transfer finish interrupt
bits : 4 - 4 (1 bit)
TFCS : Transfer flow controller select
bits : 5 - 5 (1 bit)
TM : Transfer mode
bits : 6 - 7 (2 bit)
CMEN : Circulation mode enable
bits : 8 - 8 (1 bit)
PNAGA : Next address generation algorithm of peripheral
bits : 9 - 9 (1 bit)
MNAGA : Next address generation algorithm of memory
bits : 10 - 10 (1 bit)
PWIDTH : Transfer width of peripheral
bits : 11 - 12 (2 bit)
MWIDTH : Transfer width of memory
bits : 13 - 14 (2 bit)
PAIF : Peripheral address increment fixed
bits : 15 - 15 (1 bit)
PRIO : Priority level
bits : 16 - 17 (2 bit)
SBMEN : Switch-buffer mode enable
bits : 18 - 18 (1 bit)
MBS : Memory buffer select
bits : 19 - 19 (1 bit)
PBURST : Transfer burst type of peripheral
bits : 21 - 22 (2 bit)
MBURST : Transfer burst type of memory
bits : 23 - 24 (2 bit)
PERIEN : Peripheral enable
bits : 25 - 27 (3 bit)
Channel 7 counter register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Transfer counter
bits : 0 - 15 (16 bit)
Interrupt flag clear register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FEEIFC4 : Clear bit for FIFO error and exception of channel 4
bits : 0 - 0 (1 bit)
SDEIFC4 : Clear bit for single data mode exception of channel 4
bits : 2 - 2 (1 bit)
TAEIFC4 : Clear bit for transfer access error flag of channel 4
bits : 3 - 3 (1 bit)
HTFIFC4 : Clear bit for half transfer finish flag of channel 4
bits : 4 - 4 (1 bit)
FTFIFC4 : Clear bit for Full transfer finish flag of channel 4
bits : 5 - 5 (1 bit)
FEEIFC5 : Clear bit for FIFO error and exception of channel 5
bits : 6 - 6 (1 bit)
SDEIFC5 : Clear bit for single data mode exception of channel 5
bits : 8 - 8 (1 bit)
TAEIFC5 : Clear bit for transfer access error flag of channel 5
bits : 9 - 9 (1 bit)
HTFIFC5 : Clear bit for half transfer finish flag of channel 5
bits : 10 - 10 (1 bit)
FTFIFC5 : Clear bit for Full transfer finish flag of channel 5
bits : 11 - 11 (1 bit)
FEEIFC6 : Clear bit for FIFO error and exception of channel 6
bits : 16 - 16 (1 bit)
SDEIFC6 : Clear bit for single data mode exception of channel 6
bits : 18 - 18 (1 bit)
TAEIFC6 : Clear bit for transfer access error flag of channel 6
bits : 19 - 19 (1 bit)
HTFIFC6 : Clear bit for half transfer finish flag of channel 6
bits : 20 - 20 (1 bit)
FTFIFC6 : Clear bit for Full transfer finish flag of channel 6
bits : 21 - 21 (1 bit)
FEEIFC7 : Clear bit for FIFO error and exception of channel 7
bits : 22 - 22 (1 bit)
SDEIFC7 : Clear bit for single data mode exception of channel 7
bits : 24 - 24 (1 bit)
TAEIFC7 : Clear bit for transfer access error flag of channel 7
bits : 25 - 25 (1 bit)
HTFIFC7 : Clear bit for half transfer finish flag of channel 7
bits : 26 - 26 (1 bit)
FTFIFC7 : Clear bit for Full transfer finish flag of channel 7
bits : 27 - 27 (1 bit)
Channel 7 peripheral base address register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR : Peripheral base address
bits : 0 - 31 (32 bit)
Channel 7 memory 0 base address register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0ADDR : Memory 0 base address
bits : 0 - 31 (32 bit)
Channel 7 memory 1 base address register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M1ADDR : Memory 1 base address
bits : 0 - 31 (32 bit)
Channel 7 FIFO control register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCCV : FIFO counter critical value
bits : 0 - 1 (2 bit)
MDMEN : Multi-data mode enable
bits : 2 - 2 (1 bit)
FCNT : FIFO counter
bits : 3 - 5 (3 bit)
FEEIE : Enable bit for FIFO error and exception interrupt
bits : 7 - 7 (1 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.