\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
SRAM/NOR flash control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NRBKEN : NOR bank enable
bits : 0 - 0 (1 bit)
NRMUX : NOR bank memory address/data multiplexing
bits : 1 - 1 (1 bit)
NRTP : NOR bank memory type
bits : 2 - 3 (2 bit)
NRW : NOR bank memory data bus width
bits : 4 - 5 (2 bit)
NREN : NOR Flash access enable
bits : 6 - 6 (1 bit)
SBRSTEN : Synchronous burst enable
bits : 8 - 8 (1 bit)
NRWTPOL : NWAIT signal polarity
bits : 9 - 9 (1 bit)
WRAPEN : Wrapped burst mode enable
bits : 10 - 10 (1 bit)
NRWTCFG : NWAIT signal configuration, only work in synchronous mode
bits : 11 - 11 (1 bit)
WREN : Write enable
bits : 12 - 12 (1 bit)
NRWTEN : NWAIT signal enable
bits : 13 - 13 (1 bit)
EXMODEN : Extended mode enable
bits : 14 - 14 (1 bit)
ASYNCWAIT : Asynchronous wait
bits : 15 - 15 (1 bit)
CPS : CRAM page size
bits : 16 - 18 (3 bit)
SYNCWR : Synchronous write
bits : 19 - 19 (1 bit)
CCK : Consecutive Clock
bits : 20 - 20 (1 bit)
SRAM/NOR flash control register 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NRBKEN : NOR bank enable
bits : 0 - 0 (1 bit)
NRMUX : NOR bank memory address/data multiplexing
bits : 1 - 1 (1 bit)
NRTP : NOR bank memory type
bits : 2 - 3 (2 bit)
NRW : NOR bank memory data bus width
bits : 4 - 5 (2 bit)
NREN : NOR Flash access enable
bits : 6 - 6 (1 bit)
SBRSTEN : Synchronous burst enable
bits : 8 - 8 (1 bit)
NRWTPOL : NWAIT signal polarity
bits : 9 - 9 (1 bit)
WRAPEN : Wrapped burst mode enable
bits : 10 - 10 (1 bit)
NRWTCFG : NWAIT signal configuration, only work in synchronous mode
bits : 11 - 11 (1 bit)
WREN : Write enable
bits : 12 - 12 (1 bit)
NRWTEN : NWAIT signal enable
bits : 13 - 13 (1 bit)
EXMODEN : Extended mode enable
bits : 14 - 14 (1 bit)
ASYNCWAIT : Asynchronous wait
bits : 15 - 15 (1 bit)
CPS : CRAM page size
bits : 16 - 18 (3 bit)
SYNCWR : Synchronous write
bits : 19 - 19 (1 bit)
CCK : Consecutive Clock
bits : 20 - 20 (1 bit)
SRAM/NOR flash write timing configuration register 0
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WASET : Address setup time
bits : 0 - 3 (4 bit)
WAHLD : Address hold time
bits : 4 - 7 (4 bit)
WDSET : Data setup time
bits : 8 - 15 (8 bit)
WBUSLAT : Bus latency
bits : 16 - 19 (4 bit)
WASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)
SRAM/NOR flash write timing configuration register 1
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WASET : Address setup time
bits : 0 - 3 (4 bit)
WAHLD : Address hold time
bits : 4 - 7 (4 bit)
WDSET : Data setup time
bits : 8 - 15 (8 bit)
WBUSLAT : Bus latency
bits : 16 - 19 (4 bit)
WASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)
SRAM/NOR flash write timing configuration register 2
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WASET : Address setup time
bits : 0 - 3 (4 bit)
WAHLD : Address hold time
bits : 4 - 7 (4 bit)
WDSET : Data setup time
bits : 8 - 15 (8 bit)
WBUSLAT : Bus latency
bits : 16 - 19 (4 bit)
WASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)
SRAM/NOR flash write timing configuration register 3
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WASET : Address setup time
bits : 0 - 3 (4 bit)
WAHLD : Address hold time
bits : 4 - 7 (4 bit)
WDSET : Data setup time
bits : 8 - 15 (8 bit)
WBUSLAT : Bus latency
bits : 16 - 19 (4 bit)
WASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)
SRAM/NOR flash timing configuration register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ASET : Address setup time
bits : 0 - 3 (4 bit)
AHLD : Address hold time
bits : 4 - 7 (4 bit)
DSET : Data setup time
bits : 8 - 15 (8 bit)
BUSLAT : Bus latency
bits : 16 - 19 (4 bit)
CKDIV : Synchronous clock divide ratio
bits : 20 - 23 (4 bit)
DLAT : Data latency for NOR Flash
bits : 24 - 27 (4 bit)
ASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)
SDRAM control register 0
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAW : Column address bit width
bits : 0 - 1 (2 bit)
RAW : Row address bit width
bits : 2 - 3 (2 bit)
SDW : SDRAM data bus width
bits : 4 - 5 (2 bit)
NBK : Number of banks
bits : 6 - 6 (1 bit)
CL : CAS Latency
bits : 7 - 8 (2 bit)
WPEN : Write protection enable
bits : 9 - 9 (1 bit)
SDCLK : SDRAM clock configuration
bits : 10 - 11 (2 bit)
BRSTRD : Burst read
bits : 12 - 12 (1 bit)
PIPED : Pipeline delay
bits : 13 - 14 (2 bit)
SDRAM control register 1
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAW : Column address bit width
bits : 0 - 1 (2 bit)
RAW : Row address bit width
bits : 2 - 3 (2 bit)
SDW : SDRAM data bus width
bits : 4 - 5 (2 bit)
NBK : Number of banks
bits : 6 - 6 (1 bit)
CL : CAS Latency
bits : 7 - 8 (2 bit)
WPEN : Write protection enable
bits : 9 - 9 (1 bit)
SDCLK : SDRAM clock configuration
bits : 10 - 11 (2 bit)
BRSTRD : Burst read
bits : 12 - 12 (1 bit)
PIPED : Pipeline delay
bits : 13 - 14 (2 bit)
SDRAM timing configuration register 0
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LMRD : Load Mode Register Delay
bits : 0 - 3 (4 bit)
XSRD : Exit Self-refresh delay
bits : 4 - 7 (4 bit)
RASD : Row address select delay
bits : 8 - 11 (4 bit)
ARFD : Auto refresh delay
bits : 12 - 15 (4 bit)
WRD : Write recovery delay
bits : 16 - 19 (4 bit)
RPD : Row precharge delay
bits : 20 - 23 (4 bit)
RCD : Row to column delay
bits : 24 - 27 (4 bit)
SDRAM timing configuration register 1
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LMRD : Load Mode Register Delay
bits : 0 - 3 (4 bit)
XSRD : Exit Self-refresh delay
bits : 4 - 7 (4 bit)
RASD : Row address select delay
bits : 8 - 11 (4 bit)
ARFD : Auto refresh delay
bits : 12 - 15 (4 bit)
WRD : Write recovery delay
bits : 16 - 19 (4 bit)
RPD : Row precharge delay
bits : 20 - 23 (4 bit)
RCD : Row to column delay
bits : 24 - 27 (4 bit)
SDRAM command register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Command
bits : 0 - 2 (3 bit)
DS1 : Device select 1
bits : 3 - 3 (1 bit)
DS0 : Device select 0
bits : 4 - 4 (1 bit)
NARF : Number of successive Auto-refresh
bits : 5 - 8 (4 bit)
MRC : Mode register content
bits : 9 - 21 (13 bit)
SDRAM auto-refresh interval register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REC : Refresh error flag clear
bits : 0 - 0 (1 bit)
ARINTV : Auto-Refresh Interval
bits : 1 - 13 (13 bit)
REIE : Refresh error interrupt Enable
bits : 14 - 14 (1 bit)
SDRAM status register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REIF : Refresh error interrupt flag
bits : 0 - 0 (1 bit)
access : read-write
STA0 : Device 0 status
bits : 1 - 2 (2 bit)
access : read-write
STA1 : Device1 status
bits : 3 - 4 (2 bit)
access : read-write
NRDY : Not Ready status
bits : 5 - 5 (1 bit)
access : read-write
SRAM/NOR flash control register 3
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NRBKEN : NOR bank enable
bits : 0 - 0 (1 bit)
NRMUX : NOR bank memory address/data multiplexing
bits : 1 - 1 (1 bit)
NRTP : NOR bank memory type
bits : 2 - 3 (2 bit)
NRW : NOR bank memory data bus width
bits : 4 - 5 (2 bit)
NREN : NOR Flash access enable
bits : 6 - 6 (1 bit)
SBRSTEN : Synchronous burst enable
bits : 8 - 8 (1 bit)
NRWTPOL : NWAIT signal polarity
bits : 9 - 9 (1 bit)
WRAPEN : Wrapped burst mode enable
bits : 10 - 10 (1 bit)
NRWTCFG : NWAIT signal configuration, only work in synchronous mode
bits : 11 - 11 (1 bit)
WREN : Write enable
bits : 12 - 12 (1 bit)
NRWTEN : NWAIT signal enable
bits : 13 - 13 (1 bit)
EXMODEN : Extended mode enable
bits : 14 - 14 (1 bit)
ASYNCWAIT : Asynchronous wait
bits : 15 - 15 (1 bit)
CPS : CRAM page size
bits : 16 - 18 (3 bit)
SYNCWR : Synchronous write
bits : 19 - 19 (1 bit)
CCK : Consecutive Clock
bits : 20 - 20 (1 bit)
SDRAM read sample control register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSEN : Read sample enable
bits : 0 - 0 (1 bit)
SSCR : Select sample cycle of read data
bits : 1 - 1 (1 bit)
SDSC : Select the delayed sample clock of read data
bits : 4 - 7 (4 bit)
SRAM/NOR flash timing configuration register 3
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ASET : Address setup time
bits : 0 - 3 (4 bit)
AHLD : Address hold time
bits : 4 - 7 (4 bit)
DSET : Data setup time
bits : 8 - 15 (8 bit)
BUSLAT : Bus latency
bits : 16 - 19 (4 bit)
CKDIV : Synchronous clock divide ratio
bits : 20 - 23 (4 bit)
DLAT : Data latency for NOR Flash
bits : 24 - 27 (4 bit)
ASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)
SPI initialization register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDBIT : Bit number of SPI PSRAM command phase
bits : 16 - 17 (2 bit)
ADRBIT : Bit number of SPI PSRAM address phase
bits : 24 - 28 (5 bit)
IDL : SPI PSRAM ID Length
bits : 29 - 30 (2 bit)
POL : Read data sample polarity
bits : 31 - 31 (1 bit)
SPI read command register
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCMD : SPI Read Command for AHB read transfer
bits : 0 - 15 (16 bit)
RWAITCYCLE : SPI Read Wait Cycle number after address phase
bits : 16 - 19 (4 bit)
RMODE : SPI PSRAM Read command mode
bits : 20 - 21 (2 bit)
RDID : Send SPI Read ID Command
bits : 31 - 31 (1 bit)
SPI write command register
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WCMD : SPI Write Command for AHB write transfer
bits : 0 - 14 (15 bit)
WWAITCYCLE : SPI Write Wait Cycle number after address phase
bits : 16 - 19 (4 bit)
WMODE : SPI PSRAM Write command mode
bits : 20 - 21 (2 bit)
SC : Send SPI Special Command which does not have address and data phase, command code and mode come from WCMD and WMODE
bits : 31 - 31 (1 bit)
SPI ID low register
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIDL : ID Low Data saved for SPI Read ID Command
bits : 0 - 31 (32 bit)
access : read-write
SPI ID high register
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIDH : ID High Data saved for SPI Read ID Command
bits : 0 - 31 (32 bit)
SRAM/NOR flash timing configuration register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ASET : Address setup time
bits : 0 - 3 (4 bit)
AHLD : Address hold time
bits : 4 - 7 (4 bit)
DSET : Data setup time
bits : 8 - 15 (8 bit)
BUSLAT : Bus latency
bits : 16 - 19 (4 bit)
CKDIV : Synchronous clock divide ratio
bits : 20 - 23 (4 bit)
DLAT : Data latency for NOR Flash
bits : 24 - 27 (4 bit)
ASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)
NAND flash/PC card control register 1
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDWTEN : Wait feature enable
bits : 1 - 1 (1 bit)
NDBKEN : NAND bank enable
bits : 2 - 2 (1 bit)
NDTP : NAND bank memory type
bits : 3 - 3 (1 bit)
NDW : NAND bank memory data bus width
bits : 4 - 5 (2 bit)
ECCEN : ECC enable
bits : 6 - 6 (1 bit)
CTR : CLE to RE delay
bits : 9 - 12 (4 bit)
ATR : ALE to RE delay
bits : 13 - 16 (4 bit)
ECCSZ : ECC size
bits : 17 - 19 (3 bit)
NAND flash/PC card interrupt enable register 1
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTRS : Interrupt rising edge status
bits : 0 - 0 (1 bit)
INTHS : Interrupt high-level status
bits : 1 - 1 (1 bit)
INTFS : Interrupt falling edge status
bits : 2 - 2 (1 bit)
INTREN : Interrupt rising edge detection enable bit
bits : 3 - 3 (1 bit)
INTHEN : Interrupt high-level detection enable
bits : 4 - 4 (1 bit)
INTFEN : Interrupt falling edge detection enable
bits : 5 - 5 (1 bit)
FFEPT : FIFO empty flag
bits : 6 - 6 (1 bit)
NAND flash/PC card common space timing configuration register 1
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMSET : Common memory setup time
bits : 0 - 7 (8 bit)
COMWAIT : Common memory wait time
bits : 8 - 15 (8 bit)
COMHLD : Common memory hold time
bits : 16 - 23 (8 bit)
COMHIZ : Common memory data bus HiZ time
bits : 24 - 31 (8 bit)
NAND flash/PC card attribute space timing configuration register 1
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATTSET : Attribute memory setup time
bits : 0 - 7 (8 bit)
ATTWAIT : Attribute memory wait time
bits : 8 - 15 (8 bit)
ATTHLD : Attribute memory hold time
bits : 16 - 23 (8 bit)
ATTHIZ : Attribute memory data bus HiZ time
bits : 24 - 31 (8 bit)
NAND flash ECC register 1
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC : ECC result
bits : 0 - 31 (32 bit)
access : read-only
SRAM/NOR flash control register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NRBKEN : NOR bank enable
bits : 0 - 0 (1 bit)
NRMUX : NOR bank memory address/data multiplexing
bits : 1 - 1 (1 bit)
NRTP : NOR bank memory type
bits : 2 - 3 (2 bit)
NRW : NOR bank memory data bus width
bits : 4 - 5 (2 bit)
NREN : NOR Flash access enable
bits : 6 - 6 (1 bit)
SBRSTEN : Synchronous burst enable
bits : 8 - 8 (1 bit)
NRWTPOL : NWAIT signal polarity
bits : 9 - 9 (1 bit)
WRAPEN : Wrapped burst mode enable
bits : 10 - 10 (1 bit)
NRWTCFG : NWAIT signal configuration, only work in synchronous mode
bits : 11 - 11 (1 bit)
WREN : Write enable
bits : 12 - 12 (1 bit)
NRWTEN : NWAIT signal enable
bits : 13 - 13 (1 bit)
EXMODEN : Extended mode enable
bits : 14 - 14 (1 bit)
ASYNCWAIT : Asynchronous wait
bits : 15 - 15 (1 bit)
CPS : CRAM page size
bits : 16 - 18 (3 bit)
SYNCWR : Synchronous write
bits : 19 - 19 (1 bit)
CCK : Consecutive Clock
bits : 20 - 20 (1 bit)
NAND flash/PC card control register 2
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDWTEN : Wait feature enable
bits : 1 - 1 (1 bit)
NDBKEN : NAND bank enable
bits : 2 - 2 (1 bit)
NDTP : NAND bank memory type
bits : 3 - 3 (1 bit)
NDW : NAND bank memory data bus width
bits : 4 - 5 (2 bit)
ECCEN : ECC enable
bits : 6 - 6 (1 bit)
CTR : CLE to RE delay
bits : 9 - 12 (4 bit)
ATR : ALE to RE delay
bits : 13 - 16 (4 bit)
ECCSZ : ECC size
bits : 17 - 19 (3 bit)
NAND flash/PC card interrupt enable register 2
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTRS : Interrupt rising edge status
bits : 0 - 0 (1 bit)
INTHS : Interrupt high-level status
bits : 1 - 1 (1 bit)
INTFS : Interrupt falling edge status
bits : 2 - 2 (1 bit)
INTREN : Interrupt rising edge detection enable bit
bits : 3 - 3 (1 bit)
INTHEN : Interrupt high-level detection enable
bits : 4 - 4 (1 bit)
INTFEN : Interrupt falling edge detection enable
bits : 5 - 5 (1 bit)
FFEPT : FIFO empty flag
bits : 6 - 6 (1 bit)
NAND flash/PC card common space timing configuration register 2
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMSET : Common memory setup time
bits : 0 - 7 (8 bit)
COMWAIT : Common memory wait time
bits : 8 - 15 (8 bit)
COMHLD : Common memory hold time
bits : 16 - 23 (8 bit)
COMHIZ : Common memory data bus HiZ time
bits : 24 - 31 (8 bit)
NAND flash/PC card attribute space timing configuration register 2
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATTSET : Attribute memory setup time
bits : 0 - 7 (8 bit)
ATTWAIT : Attribute memory wait time
bits : 8 - 15 (8 bit)
ATTHLD : Attribute memory hold time
bits : 16 - 23 (8 bit)
ATTHIZ : Attribute memory data bus HiZ time
bits : 24 - 31 (8 bit)
NAND flash ECC register 2
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC : ECC result
bits : 0 - 31 (32 bit)
access : read-only
NAND flash/PC card control register 3
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDWTEN : Wait feature enable
bits : 1 - 1 (1 bit)
NDBKEN : NAND bank enable
bits : 2 - 2 (1 bit)
NDTP : NAND bank memory type
bits : 3 - 3 (1 bit)
NDW : NAND bank memory data bus width
bits : 4 - 5 (2 bit)
ECCEN : ECC enable
bits : 6 - 6 (1 bit)
CTR : CLE to RE delay
bits : 9 - 12 (4 bit)
ATR : ALE to RE delay
bits : 13 - 16 (4 bit)
ECCSZ : ECC size
bits : 17 - 19 (3 bit)
NAND flash/PC card interrupt enable register 3
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTRS : Interrupt rising edge status
bits : 0 - 0 (1 bit)
INTHS : Interrupt high-level status
bits : 1 - 1 (1 bit)
INTFS : Interrupt falling edge status
bits : 2 - 2 (1 bit)
INTREN : Interrupt rising edge detection enable bit
bits : 3 - 3 (1 bit)
INTHEN : Interrupt high-level detection enable
bits : 4 - 4 (1 bit)
INTFEN : Interrupt falling edge detection enable
bits : 5 - 5 (1 bit)
FFEPT : FIFO empty flag
bits : 6 - 6 (1 bit)
NAND flash/PC card common space timing configuration register 3
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMSET : Common memory setup time
bits : 0 - 7 (8 bit)
COMWAIT : Common memory wait time
bits : 8 - 15 (8 bit)
COMHLD : Common memory hold time
bits : 16 - 23 (8 bit)
COMHIZ : Common memory data bus HiZ time
bits : 24 - 31 (8 bit)
NAND flash/PC card attribute space timing configuration register 3
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATTSET : Attribute memory setup time
bits : 0 - 7 (8 bit)
ATTWAIT : Attribute memory wait time
bits : 8 - 15 (8 bit)
ATTHLD : Attribute memory hold time
bits : 16 - 23 (8 bit)
ATTHIZ : Attribute memory data bus HiZ time
bits : 24 - 31 (8 bit)
PC card I/O space timing configuration register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSET : IO space setup time
bits : 0 - 7 (8 bit)
IOWAIT : IO space wait time
bits : 8 - 15 (8 bit)
IOHLD : IO space hold time
bits : 16 - 23 (8 bit)
IOHIZ : IO space data bus HiZ time
bits : 24 - 31 (8 bit)
SRAM/NOR flash timing configuration register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ASET : Address setup time
bits : 0 - 3 (4 bit)
AHLD : Address hold time
bits : 4 - 7 (4 bit)
DSET : Data setup time
bits : 8 - 15 (8 bit)
BUSLAT : Bus latency
bits : 16 - 19 (4 bit)
CKDIV : Synchronous clock divide ratio
bits : 20 - 23 (4 bit)
DLAT : Data latency for NOR Flash
bits : 24 - 27 (4 bit)
ASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)
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