\n

EXMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

SNCTL0

SNCTL2

SNWTCFG0

SNWTCFG1

SNWTCFG2

SNWTCFG3

SNTCFG2

SDCTL0

SDCTL1

SDTCFG0

SDTCFG1

SDCMD

SDARI

SDSTAT

SNCTL3

SDRSCTL

SNTCFG3

SINIT

SRCMD

SWCMD

SIDL

SIDH

SNTCFG0

NPCTL1

NPINTEN1

NPCTCFG1

NPATCFG1

NECC1

SNCTL1

NPCTL2

NPINTEN2

NPCTCFG2

NPATCFG2

NECC2

NPCTL3

NPINTEN3

NPCTCFG3

NPATCFG3

PIOTCFG3

SNTCFG1


SNCTL0

SRAM/NOR flash control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNCTL0 SNCTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NRBKEN NRMUX NRTP NRW NREN SBRSTEN NRWTPOL WRAPEN NRWTCFG WREN NRWTEN EXMODEN ASYNCWAIT CPS SYNCWR CCK

NRBKEN : NOR bank enable
bits : 0 - 0 (1 bit)

NRMUX : NOR bank memory address/data multiplexing
bits : 1 - 1 (1 bit)

NRTP : NOR bank memory type
bits : 2 - 3 (2 bit)

NRW : NOR bank memory data bus width
bits : 4 - 5 (2 bit)

NREN : NOR Flash access enable
bits : 6 - 6 (1 bit)

SBRSTEN : Synchronous burst enable
bits : 8 - 8 (1 bit)

NRWTPOL : NWAIT signal polarity
bits : 9 - 9 (1 bit)

WRAPEN : Wrapped burst mode enable
bits : 10 - 10 (1 bit)

NRWTCFG : NWAIT signal configuration, only work in synchronous mode
bits : 11 - 11 (1 bit)

WREN : Write enable
bits : 12 - 12 (1 bit)

NRWTEN : NWAIT signal enable
bits : 13 - 13 (1 bit)

EXMODEN : Extended mode enable
bits : 14 - 14 (1 bit)

ASYNCWAIT : Asynchronous wait
bits : 15 - 15 (1 bit)

CPS : CRAM page size
bits : 16 - 18 (3 bit)

SYNCWR : Synchronous write
bits : 19 - 19 (1 bit)

CCK : Consecutive Clock
bits : 20 - 20 (1 bit)


SNCTL2

SRAM/NOR flash control register 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNCTL2 SNCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NRBKEN NRMUX NRTP NRW NREN SBRSTEN NRWTPOL WRAPEN NRWTCFG WREN NRWTEN EXMODEN ASYNCWAIT CPS SYNCWR CCK

NRBKEN : NOR bank enable
bits : 0 - 0 (1 bit)

NRMUX : NOR bank memory address/data multiplexing
bits : 1 - 1 (1 bit)

NRTP : NOR bank memory type
bits : 2 - 3 (2 bit)

NRW : NOR bank memory data bus width
bits : 4 - 5 (2 bit)

NREN : NOR Flash access enable
bits : 6 - 6 (1 bit)

SBRSTEN : Synchronous burst enable
bits : 8 - 8 (1 bit)

NRWTPOL : NWAIT signal polarity
bits : 9 - 9 (1 bit)

WRAPEN : Wrapped burst mode enable
bits : 10 - 10 (1 bit)

NRWTCFG : NWAIT signal configuration, only work in synchronous mode
bits : 11 - 11 (1 bit)

WREN : Write enable
bits : 12 - 12 (1 bit)

NRWTEN : NWAIT signal enable
bits : 13 - 13 (1 bit)

EXMODEN : Extended mode enable
bits : 14 - 14 (1 bit)

ASYNCWAIT : Asynchronous wait
bits : 15 - 15 (1 bit)

CPS : CRAM page size
bits : 16 - 18 (3 bit)

SYNCWR : Synchronous write
bits : 19 - 19 (1 bit)

CCK : Consecutive Clock
bits : 20 - 20 (1 bit)


SNWTCFG0

SRAM/NOR flash write timing configuration register 0
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNWTCFG0 SNWTCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WASET WAHLD WDSET WBUSLAT WASYNCMOD

WASET : Address setup time
bits : 0 - 3 (4 bit)

WAHLD : Address hold time
bits : 4 - 7 (4 bit)

WDSET : Data setup time
bits : 8 - 15 (8 bit)

WBUSLAT : Bus latency
bits : 16 - 19 (4 bit)

WASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)


SNWTCFG1

SRAM/NOR flash write timing configuration register 1
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNWTCFG1 SNWTCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WASET WAHLD WDSET WBUSLAT WASYNCMOD

WASET : Address setup time
bits : 0 - 3 (4 bit)

WAHLD : Address hold time
bits : 4 - 7 (4 bit)

WDSET : Data setup time
bits : 8 - 15 (8 bit)

WBUSLAT : Bus latency
bits : 16 - 19 (4 bit)

WASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)


SNWTCFG2

SRAM/NOR flash write timing configuration register 2
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNWTCFG2 SNWTCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WASET WAHLD WDSET WBUSLAT WASYNCMOD

WASET : Address setup time
bits : 0 - 3 (4 bit)

WAHLD : Address hold time
bits : 4 - 7 (4 bit)

WDSET : Data setup time
bits : 8 - 15 (8 bit)

WBUSLAT : Bus latency
bits : 16 - 19 (4 bit)

WASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)


SNWTCFG3

SRAM/NOR flash write timing configuration register 3
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNWTCFG3 SNWTCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WASET WAHLD WDSET WBUSLAT WASYNCMOD

WASET : Address setup time
bits : 0 - 3 (4 bit)

WAHLD : Address hold time
bits : 4 - 7 (4 bit)

WDSET : Data setup time
bits : 8 - 15 (8 bit)

WBUSLAT : Bus latency
bits : 16 - 19 (4 bit)

WASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)


SNTCFG2

SRAM/NOR flash timing configuration register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNTCFG2 SNTCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASET AHLD DSET BUSLAT CKDIV DLAT ASYNCMOD

ASET : Address setup time
bits : 0 - 3 (4 bit)

AHLD : Address hold time
bits : 4 - 7 (4 bit)

DSET : Data setup time
bits : 8 - 15 (8 bit)

BUSLAT : Bus latency
bits : 16 - 19 (4 bit)

CKDIV : Synchronous clock divide ratio
bits : 20 - 23 (4 bit)

DLAT : Data latency for NOR Flash
bits : 24 - 27 (4 bit)

ASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)


SDCTL0

SDRAM control register 0
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDCTL0 SDCTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAW RAW SDW NBK CL WPEN SDCLK BRSTRD PIPED

CAW : Column address bit width
bits : 0 - 1 (2 bit)

RAW : Row address bit width
bits : 2 - 3 (2 bit)

SDW : SDRAM data bus width
bits : 4 - 5 (2 bit)

NBK : Number of banks
bits : 6 - 6 (1 bit)

CL : CAS Latency
bits : 7 - 8 (2 bit)

WPEN : Write protection enable
bits : 9 - 9 (1 bit)

SDCLK : SDRAM clock configuration
bits : 10 - 11 (2 bit)

BRSTRD : Burst read
bits : 12 - 12 (1 bit)

PIPED : Pipeline delay
bits : 13 - 14 (2 bit)


SDCTL1

SDRAM control register 1
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDCTL1 SDCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAW RAW SDW NBK CL WPEN SDCLK BRSTRD PIPED

CAW : Column address bit width
bits : 0 - 1 (2 bit)

RAW : Row address bit width
bits : 2 - 3 (2 bit)

SDW : SDRAM data bus width
bits : 4 - 5 (2 bit)

NBK : Number of banks
bits : 6 - 6 (1 bit)

CL : CAS Latency
bits : 7 - 8 (2 bit)

WPEN : Write protection enable
bits : 9 - 9 (1 bit)

SDCLK : SDRAM clock configuration
bits : 10 - 11 (2 bit)

BRSTRD : Burst read
bits : 12 - 12 (1 bit)

PIPED : Pipeline delay
bits : 13 - 14 (2 bit)


SDTCFG0

SDRAM timing configuration register 0
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDTCFG0 SDTCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LMRD XSRD RASD ARFD WRD RPD RCD

LMRD : Load Mode Register Delay
bits : 0 - 3 (4 bit)

XSRD : Exit Self-refresh delay
bits : 4 - 7 (4 bit)

RASD : Row address select delay
bits : 8 - 11 (4 bit)

ARFD : Auto refresh delay
bits : 12 - 15 (4 bit)

WRD : Write recovery delay
bits : 16 - 19 (4 bit)

RPD : Row precharge delay
bits : 20 - 23 (4 bit)

RCD : Row to column delay
bits : 24 - 27 (4 bit)


SDTCFG1

SDRAM timing configuration register 1
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDTCFG1 SDTCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LMRD XSRD RASD ARFD WRD RPD RCD

LMRD : Load Mode Register Delay
bits : 0 - 3 (4 bit)

XSRD : Exit Self-refresh delay
bits : 4 - 7 (4 bit)

RASD : Row address select delay
bits : 8 - 11 (4 bit)

ARFD : Auto refresh delay
bits : 12 - 15 (4 bit)

WRD : Write recovery delay
bits : 16 - 19 (4 bit)

RPD : Row precharge delay
bits : 20 - 23 (4 bit)

RCD : Row to column delay
bits : 24 - 27 (4 bit)


SDCMD

SDRAM command register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDCMD SDCMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD DS1 DS0 NARF MRC

CMD : Command
bits : 0 - 2 (3 bit)

DS1 : Device select 1
bits : 3 - 3 (1 bit)

DS0 : Device select 0
bits : 4 - 4 (1 bit)

NARF : Number of successive Auto-refresh
bits : 5 - 8 (4 bit)

MRC : Mode register content
bits : 9 - 21 (13 bit)


SDARI

SDRAM auto-refresh interval register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDARI SDARI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REC ARINTV REIE

REC : Refresh error flag clear
bits : 0 - 0 (1 bit)

ARINTV : Auto-Refresh Interval
bits : 1 - 13 (13 bit)

REIE : Refresh error interrupt Enable
bits : 14 - 14 (1 bit)


SDSTAT

SDRAM status register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDSTAT SDSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REIF STA0 STA1 NRDY

REIF : Refresh error interrupt flag
bits : 0 - 0 (1 bit)
access : read-write

STA0 : Device 0 status
bits : 1 - 2 (2 bit)
access : read-write

STA1 : Device1 status
bits : 3 - 4 (2 bit)
access : read-write

NRDY : Not Ready status
bits : 5 - 5 (1 bit)
access : read-write


SNCTL3

SRAM/NOR flash control register 3
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNCTL3 SNCTL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NRBKEN NRMUX NRTP NRW NREN SBRSTEN NRWTPOL WRAPEN NRWTCFG WREN NRWTEN EXMODEN ASYNCWAIT CPS SYNCWR CCK

NRBKEN : NOR bank enable
bits : 0 - 0 (1 bit)

NRMUX : NOR bank memory address/data multiplexing
bits : 1 - 1 (1 bit)

NRTP : NOR bank memory type
bits : 2 - 3 (2 bit)

NRW : NOR bank memory data bus width
bits : 4 - 5 (2 bit)

NREN : NOR Flash access enable
bits : 6 - 6 (1 bit)

SBRSTEN : Synchronous burst enable
bits : 8 - 8 (1 bit)

NRWTPOL : NWAIT signal polarity
bits : 9 - 9 (1 bit)

WRAPEN : Wrapped burst mode enable
bits : 10 - 10 (1 bit)

NRWTCFG : NWAIT signal configuration, only work in synchronous mode
bits : 11 - 11 (1 bit)

WREN : Write enable
bits : 12 - 12 (1 bit)

NRWTEN : NWAIT signal enable
bits : 13 - 13 (1 bit)

EXMODEN : Extended mode enable
bits : 14 - 14 (1 bit)

ASYNCWAIT : Asynchronous wait
bits : 15 - 15 (1 bit)

CPS : CRAM page size
bits : 16 - 18 (3 bit)

SYNCWR : Synchronous write
bits : 19 - 19 (1 bit)

CCK : Consecutive Clock
bits : 20 - 20 (1 bit)


SDRSCTL

SDRAM read sample control register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDRSCTL SDRSCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSEN SSCR SDSC

RSEN : Read sample enable
bits : 0 - 0 (1 bit)

SSCR : Select sample cycle of read data
bits : 1 - 1 (1 bit)

SDSC : Select the delayed sample clock of read data
bits : 4 - 7 (4 bit)


SNTCFG3

SRAM/NOR flash timing configuration register 3
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNTCFG3 SNTCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASET AHLD DSET BUSLAT CKDIV DLAT ASYNCMOD

ASET : Address setup time
bits : 0 - 3 (4 bit)

AHLD : Address hold time
bits : 4 - 7 (4 bit)

DSET : Data setup time
bits : 8 - 15 (8 bit)

BUSLAT : Bus latency
bits : 16 - 19 (4 bit)

CKDIV : Synchronous clock divide ratio
bits : 20 - 23 (4 bit)

DLAT : Data latency for NOR Flash
bits : 24 - 27 (4 bit)

ASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)


SINIT

SPI initialization register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SINIT SINIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDBIT ADRBIT IDL POL

CMDBIT : Bit number of SPI PSRAM command phase
bits : 16 - 17 (2 bit)

ADRBIT : Bit number of SPI PSRAM address phase
bits : 24 - 28 (5 bit)

IDL : SPI PSRAM ID Length
bits : 29 - 30 (2 bit)

POL : Read data sample polarity
bits : 31 - 31 (1 bit)


SRCMD

SPI read command register
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRCMD SRCMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCMD RWAITCYCLE RMODE RDID

RCMD : SPI Read Command for AHB read transfer
bits : 0 - 15 (16 bit)

RWAITCYCLE : SPI Read Wait Cycle number after address phase
bits : 16 - 19 (4 bit)

RMODE : SPI PSRAM Read command mode
bits : 20 - 21 (2 bit)

RDID : Send SPI Read ID Command
bits : 31 - 31 (1 bit)


SWCMD

SPI write command register
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWCMD SWCMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WCMD WWAITCYCLE WMODE SC

WCMD : SPI Write Command for AHB write transfer
bits : 0 - 14 (15 bit)

WWAITCYCLE : SPI Write Wait Cycle number after address phase
bits : 16 - 19 (4 bit)

WMODE : SPI PSRAM Write command mode
bits : 20 - 21 (2 bit)

SC : Send SPI Special Command which does not have address and data phase, command code and mode come from WCMD and WMODE
bits : 31 - 31 (1 bit)


SIDL

SPI ID low register
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIDL SIDL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIDL

SIDL : ID Low Data saved for SPI Read ID Command
bits : 0 - 31 (32 bit)
access : read-write


SIDH

SPI ID high register
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIDH SIDH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIDH

SIDH : ID High Data saved for SPI Read ID Command
bits : 0 - 31 (32 bit)


SNTCFG0

SRAM/NOR flash timing configuration register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNTCFG0 SNTCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASET AHLD DSET BUSLAT CKDIV DLAT ASYNCMOD

ASET : Address setup time
bits : 0 - 3 (4 bit)

AHLD : Address hold time
bits : 4 - 7 (4 bit)

DSET : Data setup time
bits : 8 - 15 (8 bit)

BUSLAT : Bus latency
bits : 16 - 19 (4 bit)

CKDIV : Synchronous clock divide ratio
bits : 20 - 23 (4 bit)

DLAT : Data latency for NOR Flash
bits : 24 - 27 (4 bit)

ASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)


NPCTL1

NAND flash/PC card control register 1
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPCTL1 NPCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDWTEN NDBKEN NDTP NDW ECCEN CTR ATR ECCSZ

NDWTEN : Wait feature enable
bits : 1 - 1 (1 bit)

NDBKEN : NAND bank enable
bits : 2 - 2 (1 bit)

NDTP : NAND bank memory type
bits : 3 - 3 (1 bit)

NDW : NAND bank memory data bus width
bits : 4 - 5 (2 bit)

ECCEN : ECC enable
bits : 6 - 6 (1 bit)

CTR : CLE to RE delay
bits : 9 - 12 (4 bit)

ATR : ALE to RE delay
bits : 13 - 16 (4 bit)

ECCSZ : ECC size
bits : 17 - 19 (3 bit)


NPINTEN1

NAND flash/PC card interrupt enable register 1
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPINTEN1 NPINTEN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTRS INTHS INTFS INTREN INTHEN INTFEN FFEPT

INTRS : Interrupt rising edge status
bits : 0 - 0 (1 bit)

INTHS : Interrupt high-level status
bits : 1 - 1 (1 bit)

INTFS : Interrupt falling edge status
bits : 2 - 2 (1 bit)

INTREN : Interrupt rising edge detection enable bit
bits : 3 - 3 (1 bit)

INTHEN : Interrupt high-level detection enable
bits : 4 - 4 (1 bit)

INTFEN : Interrupt falling edge detection enable
bits : 5 - 5 (1 bit)

FFEPT : FIFO empty flag
bits : 6 - 6 (1 bit)


NPCTCFG1

NAND flash/PC card common space timing configuration register 1
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPCTCFG1 NPCTCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMSET COMWAIT COMHLD COMHIZ

COMSET : Common memory setup time
bits : 0 - 7 (8 bit)

COMWAIT : Common memory wait time
bits : 8 - 15 (8 bit)

COMHLD : Common memory hold time
bits : 16 - 23 (8 bit)

COMHIZ : Common memory data bus HiZ time
bits : 24 - 31 (8 bit)


NPATCFG1

NAND flash/PC card attribute space timing configuration register 1
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPATCFG1 NPATCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATTSET ATTWAIT ATTHLD ATTHIZ

ATTSET : Attribute memory setup time
bits : 0 - 7 (8 bit)

ATTWAIT : Attribute memory wait time
bits : 8 - 15 (8 bit)

ATTHLD : Attribute memory hold time
bits : 16 - 23 (8 bit)

ATTHIZ : Attribute memory data bus HiZ time
bits : 24 - 31 (8 bit)


NECC1

NAND flash ECC register 1
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NECC1 NECC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECC

ECC : ECC result
bits : 0 - 31 (32 bit)
access : read-only


SNCTL1

SRAM/NOR flash control register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNCTL1 SNCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NRBKEN NRMUX NRTP NRW NREN SBRSTEN NRWTPOL WRAPEN NRWTCFG WREN NRWTEN EXMODEN ASYNCWAIT CPS SYNCWR CCK

NRBKEN : NOR bank enable
bits : 0 - 0 (1 bit)

NRMUX : NOR bank memory address/data multiplexing
bits : 1 - 1 (1 bit)

NRTP : NOR bank memory type
bits : 2 - 3 (2 bit)

NRW : NOR bank memory data bus width
bits : 4 - 5 (2 bit)

NREN : NOR Flash access enable
bits : 6 - 6 (1 bit)

SBRSTEN : Synchronous burst enable
bits : 8 - 8 (1 bit)

NRWTPOL : NWAIT signal polarity
bits : 9 - 9 (1 bit)

WRAPEN : Wrapped burst mode enable
bits : 10 - 10 (1 bit)

NRWTCFG : NWAIT signal configuration, only work in synchronous mode
bits : 11 - 11 (1 bit)

WREN : Write enable
bits : 12 - 12 (1 bit)

NRWTEN : NWAIT signal enable
bits : 13 - 13 (1 bit)

EXMODEN : Extended mode enable
bits : 14 - 14 (1 bit)

ASYNCWAIT : Asynchronous wait
bits : 15 - 15 (1 bit)

CPS : CRAM page size
bits : 16 - 18 (3 bit)

SYNCWR : Synchronous write
bits : 19 - 19 (1 bit)

CCK : Consecutive Clock
bits : 20 - 20 (1 bit)


NPCTL2

NAND flash/PC card control register 2
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPCTL2 NPCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDWTEN NDBKEN NDTP NDW ECCEN CTR ATR ECCSZ

NDWTEN : Wait feature enable
bits : 1 - 1 (1 bit)

NDBKEN : NAND bank enable
bits : 2 - 2 (1 bit)

NDTP : NAND bank memory type
bits : 3 - 3 (1 bit)

NDW : NAND bank memory data bus width
bits : 4 - 5 (2 bit)

ECCEN : ECC enable
bits : 6 - 6 (1 bit)

CTR : CLE to RE delay
bits : 9 - 12 (4 bit)

ATR : ALE to RE delay
bits : 13 - 16 (4 bit)

ECCSZ : ECC size
bits : 17 - 19 (3 bit)


NPINTEN2

NAND flash/PC card interrupt enable register 2
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPINTEN2 NPINTEN2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTRS INTHS INTFS INTREN INTHEN INTFEN FFEPT

INTRS : Interrupt rising edge status
bits : 0 - 0 (1 bit)

INTHS : Interrupt high-level status
bits : 1 - 1 (1 bit)

INTFS : Interrupt falling edge status
bits : 2 - 2 (1 bit)

INTREN : Interrupt rising edge detection enable bit
bits : 3 - 3 (1 bit)

INTHEN : Interrupt high-level detection enable
bits : 4 - 4 (1 bit)

INTFEN : Interrupt falling edge detection enable
bits : 5 - 5 (1 bit)

FFEPT : FIFO empty flag
bits : 6 - 6 (1 bit)


NPCTCFG2

NAND flash/PC card common space timing configuration register 2
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPCTCFG2 NPCTCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMSET COMWAIT COMHLD COMHIZ

COMSET : Common memory setup time
bits : 0 - 7 (8 bit)

COMWAIT : Common memory wait time
bits : 8 - 15 (8 bit)

COMHLD : Common memory hold time
bits : 16 - 23 (8 bit)

COMHIZ : Common memory data bus HiZ time
bits : 24 - 31 (8 bit)


NPATCFG2

NAND flash/PC card attribute space timing configuration register 2
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPATCFG2 NPATCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATTSET ATTWAIT ATTHLD ATTHIZ

ATTSET : Attribute memory setup time
bits : 0 - 7 (8 bit)

ATTWAIT : Attribute memory wait time
bits : 8 - 15 (8 bit)

ATTHLD : Attribute memory hold time
bits : 16 - 23 (8 bit)

ATTHIZ : Attribute memory data bus HiZ time
bits : 24 - 31 (8 bit)


NECC2

NAND flash ECC register 2
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NECC2 NECC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECC

ECC : ECC result
bits : 0 - 31 (32 bit)
access : read-only


NPCTL3

NAND flash/PC card control register 3
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPCTL3 NPCTL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDWTEN NDBKEN NDTP NDW ECCEN CTR ATR ECCSZ

NDWTEN : Wait feature enable
bits : 1 - 1 (1 bit)

NDBKEN : NAND bank enable
bits : 2 - 2 (1 bit)

NDTP : NAND bank memory type
bits : 3 - 3 (1 bit)

NDW : NAND bank memory data bus width
bits : 4 - 5 (2 bit)

ECCEN : ECC enable
bits : 6 - 6 (1 bit)

CTR : CLE to RE delay
bits : 9 - 12 (4 bit)

ATR : ALE to RE delay
bits : 13 - 16 (4 bit)

ECCSZ : ECC size
bits : 17 - 19 (3 bit)


NPINTEN3

NAND flash/PC card interrupt enable register 3
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPINTEN3 NPINTEN3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTRS INTHS INTFS INTREN INTHEN INTFEN FFEPT

INTRS : Interrupt rising edge status
bits : 0 - 0 (1 bit)

INTHS : Interrupt high-level status
bits : 1 - 1 (1 bit)

INTFS : Interrupt falling edge status
bits : 2 - 2 (1 bit)

INTREN : Interrupt rising edge detection enable bit
bits : 3 - 3 (1 bit)

INTHEN : Interrupt high-level detection enable
bits : 4 - 4 (1 bit)

INTFEN : Interrupt falling edge detection enable
bits : 5 - 5 (1 bit)

FFEPT : FIFO empty flag
bits : 6 - 6 (1 bit)


NPCTCFG3

NAND flash/PC card common space timing configuration register 3
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPCTCFG3 NPCTCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMSET COMWAIT COMHLD COMHIZ

COMSET : Common memory setup time
bits : 0 - 7 (8 bit)

COMWAIT : Common memory wait time
bits : 8 - 15 (8 bit)

COMHLD : Common memory hold time
bits : 16 - 23 (8 bit)

COMHIZ : Common memory data bus HiZ time
bits : 24 - 31 (8 bit)


NPATCFG3

NAND flash/PC card attribute space timing configuration register 3
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NPATCFG3 NPATCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATTSET ATTWAIT ATTHLD ATTHIZ

ATTSET : Attribute memory setup time
bits : 0 - 7 (8 bit)

ATTWAIT : Attribute memory wait time
bits : 8 - 15 (8 bit)

ATTHLD : Attribute memory hold time
bits : 16 - 23 (8 bit)

ATTHIZ : Attribute memory data bus HiZ time
bits : 24 - 31 (8 bit)


PIOTCFG3

PC card I/O space timing configuration register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIOTCFG3 PIOTCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSET IOWAIT IOHLD IOHIZ

IOSET : IO space setup time
bits : 0 - 7 (8 bit)

IOWAIT : IO space wait time
bits : 8 - 15 (8 bit)

IOHLD : IO space hold time
bits : 16 - 23 (8 bit)

IOHIZ : IO space data bus HiZ time
bits : 24 - 31 (8 bit)


SNTCFG1

SRAM/NOR flash timing configuration register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNTCFG1 SNTCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASET AHLD DSET BUSLAT CKDIV DLAT ASYNCMOD

ASET : Address setup time
bits : 0 - 3 (4 bit)

AHLD : Address hold time
bits : 4 - 7 (4 bit)

DSET : Data setup time
bits : 8 - 15 (8 bit)

BUSLAT : Bus latency
bits : 16 - 19 (4 bit)

CKDIV : Synchronous clock divide ratio
bits : 20 - 23 (4 bit)

DLAT : Data latency for NOR Flash
bits : 24 - 27 (4 bit)

ASYNCMOD : Asynchronous access mode
bits : 28 - 29 (2 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.