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FMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

WS

CTL

PID

OBCTL0

OBCTL1

KEY

OBKEY

STAT

WSEN


WS

wait state counter register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WS WS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WSCNT

WSCNT : wait state counter register
bits : 0 - 3 (4 bit)


CTL

Control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PG SER MER0 SN PSZ MER1 START ENDIE ERRIE LK

PG : main flash program command bit
bits : 0 - 0 (1 bit)

SER : main flash sector erase command bit
bits : 1 - 1 (1 bit)

MER0 : main flash mass erase for bank0 command bit
bits : 2 - 2 (1 bit)

SN : Select which sector number to be erased.
bits : 3 - 7 (5 bit)

PSZ : Program size bit
bits : 8 - 9 (2 bit)

MER1 : main flash mass erase for bank1command bit
bits : 15 - 15 (1 bit)

START : send erase command to FMC bit
bits : 16 - 16 (1 bit)

ENDIE : End of operation interrupt enable bit
bits : 24 - 24 (1 bit)

ERRIE : Error interrupt enable bit
bits : 25 - 25 (1 bit)

LK : FMC_CTL lock bit
bits : 31 - 31 (1 bit)


PID

Product ID register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID PID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : Product reserved ID code register
bits : 0 - 31 (32 bit)


OBCTL0

Option byte control register 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OBCTL0 OBCTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OB_LK OB_START BOR_TH BB nWDG_HW nRST_DPSLP nRST_STDBY SPC WP0 DBS DRP

OB_LK : FMC_OBCTL0 lock bit
bits : 0 - 0 (1 bit)

OB_START : send option byte change command to FMC bit
bits : 1 - 1 (1 bit)

BOR_TH : option byte BOR threshold value
bits : 2 - 3 (2 bit)

BB : option byte boot bank value
bits : 4 - 4 (1 bit)

nWDG_HW : option byte watchdog value
bits : 5 - 5 (1 bit)

nRST_DPSLP : option byte deepsleep reset value
bits : 6 - 6 (1 bit)

nRST_STDBY : option byte standby reset value
bits : 7 - 7 (1 bit)

SPC : option byte Security Protection code
bits : 8 - 15 (8 bit)

WP0 : Erase/program protection of each sector when DRP is 0
bits : 16 - 27 (12 bit)

DBS : Double banks or single bank selection when flash size is 1M
bits : 30 - 30 (1 bit)

DRP : D-bus read protection bit
bits : 31 - 31 (1 bit)


OBCTL1

Option byte control register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OBCTL1 OBCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WP1

WP1 : Erase/program protection of each sector when DRP is 0
bits : 16 - 27 (12 bit)


KEY

Unlock key register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY KEY write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : FMC_CTL unlock register
bits : 0 - 31 (32 bit)


OBKEY

Option byte unlock key register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OBKEY OBKEY write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OBKEY

OBKEY : FMC_ OBCTL0 option byte operation unlock register
bits : 0 - 31 (32 bit)


STAT

Status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 END OPERR WPERR PGMERR PGSERR RDDERR BUSY

END : End of operation flag bit
bits : 0 - 0 (1 bit)
access : read-write

OPERR : Flash operation error flag bit
bits : 1 - 1 (1 bit)
access : read-write

WPERR : Erase/Program protection error flag bit
bits : 4 - 4 (1 bit)
access : read-write

PGMERR : Program size not match error flag bit
bits : 6 - 6 (1 bit)
access : read-write

PGSERR : Program sequence error flag bit
bits : 7 - 7 (1 bit)
access : read-write

RDDERR : Read D-bus protection error flag bit
bits : 8 - 8 (1 bit)
access : read-write

BUSY : The flash is busy bit
bits : 16 - 16 (1 bit)
access : read-only


WSEN

Wait state enable register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WSEN WSEN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WSEN

WSEN : FMC wait state enable register
bits : 0 - 0 (1 bit)



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