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address_offset : 0x0 Bytes (0x0)
size : 0xC00 byte (0x0)
mem_usage : registers
protection :
Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEN : Transfer enable
bits : 0 - 0 (1 bit)
THU : Transfer hang up
bits : 1 - 1 (1 bit)
TST : Transfer stop
bits : 2 - 2 (1 bit)
TAEIE : Enable bit for transfer access error interrupt
bits : 8 - 8 (1 bit)
FTFIE : Enable bit for full transfer finish interrupt
bits : 9 - 9 (1 bit)
TLMIE : Enable bit for transfer line mark interrupt
bits : 10 - 10 (1 bit)
LACIE : Enable bit for LUT access conflict interrupt
bits : 11 - 11 (1 bit)
LLFIE : Enable bit for LUT loading finish interrupt
bits : 12 - 12 (1 bit)
WCFIE : Enable bit for wrong configuration interrupt
bits : 13 - 13 (1 bit)
PFCM : Pixel format convert mode
bits : 16 - 17 (2 bit)
Foreground line offset register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLOFF : Foreground line offset
bits : 0 - 13 (14 bit)
Background memory base address register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BMADDR : Background memory base address
bits : 0 - 31 (32 bit)
Background line offset register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLOFF : Background line offset
bits : 0 - 13 (14 bit)
Foreground pixel control register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPF : Foreground pixel format
bits : 0 - 3 (4 bit)
FLPF : Foreground LUT pixel format
bits : 4 - 4 (1 bit)
FLLEN : Foreground LUT loading enable
bits : 5 - 5 (1 bit)
FCNP : Foreground LUT number of pixel
bits : 8 - 15 (8 bit)
FAVCA : Foreground alpha value calculation algorithm
bits : 16 - 17 (2 bit)
FPDAV : Foreground pre- defined alpha value
bits : 24 - 31 (8 bit)
Foreground pixel value register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPDBV : Foreground pre-defined blue value
bits : 0 - 7 (8 bit)
FPDGV : Foreground pre-defined green value
bits : 8 - 15 (8 bit)
FPDRV : Foreground pre-defined red value
bits : 16 - 23 (8 bit)
Background pixel control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPF : Background pixel format
bits : 0 - 3 (4 bit)
BLPF : Background LUT pixel format
bits : 4 - 4 (1 bit)
BLLEN : Background LUT loading enable
bits : 5 - 5 (1 bit)
BCNP : Background LUT number of pixel
bits : 8 - 15 (8 bit)
BAVCA : Background alpha value calculation algorithm
bits : 16 - 17 (2 bit)
BPDAV : Background pre- defined alpha value
bits : 24 - 31 (8 bit)
Background pixel value register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPDBV : Background pre-defined blue value
bits : 0 - 7 (8 bit)
BPDGV : Background pre-defined green value
bits : 8 - 15 (8 bit)
BPDRV : Background pre-defined red value
bits : 16 - 23 (8 bit)
Foreground LUT memory base address register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLMBADDR : Foreground LUT memory base address
bits : 0 - 31 (32 bit)
Background LUT memory base address register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLMADDR : Background LUT memory base address
bits : 0 - 31 (32 bit)
Destination pixel control register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPF : Destination pixel format
bits : 0 - 2 (3 bit)
Destination pixel value register(When the destination pixel format is ARGB8888)
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPDBV : Destination pre-defined blue value
bits : 0 - 7 (8 bit)
DPDGV : Destination pre-defined green value
bits : 8 - 15 (8 bit)
DPDRV : Destination pre-defined red value
bits : 16 - 23 (8 bit)
DPDAV : Destination pre-defined alpha value
bits : 24 - 31 (8 bit)
Destination pixel value register(When the destination pixel format is RGB888)
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : IPA_DPV_ARGB8888
reset_Mask : 0x0
DPDBV : Destination pre-defined blue value
bits : 0 - 7 (8 bit)
DPDGV : Destination pre-defined green value
bits : 8 - 15 (8 bit)
DPDRV : Destination pre-defined red value
bits : 16 - 23 (8 bit)
Destination pixel value register(When the destination pixel format is RGB565)
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : IPA_DPV_ARGB8888
reset_Mask : 0x0
DPDBV : Destination pre-defined blue value
bits : 0 - 4 (5 bit)
DPDGV : Destination pre-defined green value
bits : 5 - 10 (6 bit)
DPDRV : Destination pre-defined red value
bits : 11 - 15 (5 bit)
Destination pixel value register(When the destination pixel format is ARGB1555)
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : IPA_DPV_ARGB8888
reset_Mask : 0x0
DPDBV : Destination pre-defined blue value
bits : 0 - 4 (5 bit)
DPDGV : Destination pre-defined green value
bits : 5 - 9 (5 bit)
DPDRV : Destination pre-defined red value
bits : 10 - 14 (5 bit)
DPDAV : Destination pre-defined alpha value
bits : 15 - 15 (1 bit)
Destination pixel value register(When the destination pixel format is ARGB4444,)
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : IPA_DPV_ARGB8888
reset_Mask : 0x0
DPDBV : Destination pre-defined blue value
bits : 0 - 3 (4 bit)
DPDGV : Destination pre-defined green value
bits : 4 - 7 (4 bit)
DPDRV : Destination pre-defined red value
bits : 8 - 11 (4 bit)
DPDAV : Destination pre-defined alpha value
bits : 12 - 15 (4 bit)
Destination memory base address register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMADDR : Destination memory base address
bits : 0 - 31 (32 bit)
Interrupt flag register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TAEIF : Transfer access error interrupt flag
bits : 0 - 0 (1 bit)
FTFIF : Full transfer finish interrupt flag
bits : 1 - 1 (1 bit)
TLMIF : Transfer line mark interrupt flag
bits : 2 - 2 (1 bit)
LACIF : LUT access conflict interrupt flag
bits : 3 - 3 (1 bit)
LLFIF : LUT loading finish interrupt flag
bits : 4 - 4 (1 bit)
WCFIF : Wrong configuration interrupt flag
bits : 5 - 5 (1 bit)
Destination line offset register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLOFF : Destination line offset
bits : 0 - 13 (14 bit)
Image size register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HEIGHT : Height of the image to be processed
bits : 0 - 15 (16 bit)
WIDTH : Width of the image to be processed
bits : 16 - 29 (14 bit)
Line mark register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LM : line mark
bits : 0 - 15 (16 bit)
Inter-timer control register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITEN : Inter-timer enable
bits : 0 - 0 (1 bit)
NCCI : Number of clock cycles interval
bits : 8 - 15 (8 bit)
Interrupt flag clear register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TAEIFC : Clear bit for transfer access error interrupt flag
bits : 0 - 0 (1 bit)
TFIFC : Clear bit for full transfer finish interrupt flag
bits : 1 - 1 (1 bit)
TLMIF : Clear bit for transfer line mark interrupt flag
bits : 2 - 2 (1 bit)
LACIFC : Clear bit for LUT access conflict interrupt flag
bits : 3 - 3 (1 bit)
LLFIFC : Clear bit for LUT loading finish interrupt flag
bits : 4 - 4 (1 bit)
CWCFIF : Clear bit for wrong configuration interrupt flag
bits : 5 - 5 (1 bit)
Foreground memory base address register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FMADDR : Foreground memory base address
bits : 0 - 31 (32 bit)
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