\n

IREF

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTL


CTL

control register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSDT SCMOD CPT SSEL CREN

CSDT : Current step data
bits : 0 - 5 (6 bit)
access : read-write

SCMOD : Sink current mode
bits : 7 - 7 (1 bit)
access : read-write

CPT : Current precision trim
bits : 8 - 12 (5 bit)
access : read-write

SSEL : Step selection
bits : 14 - 14 (1 bit)
access : read-write

CREN : Current reference enable
bits : 15 - 15 (1 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.