CTL

AHB1RST

VKEY

DSV

AHB2RST

AHB3RST

APB1RST

APB2RST

AHB1EN

AHB2EN

AHB3EN

PLL

APB1EN

APB2EN

AHB1SPEN

AHB2SPEN

AHB3SPEN

APB1SPEN

APB2SPEN

BDCTL

RSTSCK

CFG0

PLLSSCTL

PLLI2S

PLLSAI

CFG1

INT

ADDCTL

ADDINT

ADDAPB1RST

ADDAPB1EN

ADDAPB1SPEN

IRC16MEN : Internal 16MHz RC oscillator Enable
bits : 0 - 0 (1 bit)
access : read-write

IRC16MSTB : IRC16M Internal 16MHz RC Oscillator stabilization Flag
bits : 1 - 1 (1 bit)
access : read-only

IRC16MADJ : Internal 16MHz RC Oscillator clock trim adjust value
bits : 3 - 7 (5 bit)
access : read-write

IRC16MCALIB : Internal 16MHz RC Oscillator calibration value register
bits : 8 - 15 (8 bit)
access : read-only

HXTALEN : External High Speed oscillator Enable
bits : 16 - 16 (1 bit)
access : read-write

HXTALSTB : External crystal oscillator (HXTAL) clock stabilization flag
bits : 17 - 17 (1 bit)
access : read-only

HXTALBPS : External crystal oscillator (HXTAL) clock bypass mode enable
bits : 18 - 18 (1 bit)
access : read-write

CKMEN : HXTAL Clock Monitor Enable
bits : 19 - 19 (1 bit)
access : read-write

PLLEN : PLL enable
bits : 24 - 24 (1 bit)
access : read-write

PLLSTB : PLL Clock Stabilization Flag
bits : 25 - 25 (1 bit)
access : read-only

PLLI2SEN : PLLI2S enable
bits : 26 - 26 (1 bit)
access : read-write

PLLI2SSTB : PLLI2S Clock Stabilization Flag
bits : 27 - 27 (1 bit)
access : read-only

PLLSAIEN : PLLSAI enable
bits : 28 - 28 (1 bit)
access : read-write

PLLSAISTB : PLLSAI Clock Stabilization Flag
bits : 29 - 29 (1 bit)
access : read-only

PARST : GPIO port A reset
bits : 0 - 0 (1 bit)

PBRST : GPIO port B reset
bits : 1 - 1 (1 bit)

PCRST : GPIO port C reset
bits : 2 - 2 (1 bit)

PDRST : GPIO port D reset
bits : 3 - 3 (1 bit)

PERST : GPIO port E reset
bits : 4 - 4 (1 bit)

PFRST : GPIO port F reset
bits : 5 - 5 (1 bit)

PGRST : GPIO port G reset
bits : 6 - 6 (1 bit)

PHRST : GPIO port H reset
bits : 7 - 7 (1 bit)

PIRST : GPIO port I reset
bits : 8 - 8 (1 bit)

CRCRST : CRC reset
bits : 12 - 12 (1 bit)

DMA0RST : DMA0 reset
bits : 21 - 21 (1 bit)

DMA1RST : DMA1 reset
bits : 22 - 22 (1 bit)

IPARST : IPA reset
bits : 23 - 23 (1 bit)

ENETRST : Ethernet reset
bits : 25 - 25 (1 bit)

USBHSRST : USBHS reset
bits : 29 - 29 (1 bit)

KEY : The key of RCU_DSV registe
bits : 0 - 31 (32 bit)
access : write

DSLPVS : Deep-sleep mode voltage select
bits : 0 - 2 (3 bit)
access : read-write

DCIRST : DCI reset
bits : 0 - 0 (1 bit)

TRNGRST : TRNG reset
bits : 6 - 6 (1 bit)

USBFSRST : USBFS reset
bits : 7 - 7 (1 bit)

EXMCRST : EXMC reset
bits : 0 - 0 (1 bit)

TIMER1RST : TIMER1 timer reset
bits : 0 - 0 (1 bit)

TIMER2RST : TIMER2 timer reset
bits : 1 - 1 (1 bit)

TIMER3RST : TIMER3 timer reset
bits : 2 - 2 (1 bit)

TIMER4RST : TIMER4 timer reset
bits : 3 - 3 (1 bit)

TIMER5RST : TIMER5 timer reset
bits : 4 - 4 (1 bit)

TIMER6RST : TIMER6 timer reset
bits : 5 - 5 (1 bit)

TIMER11RST : TIMER11 timer reset
bits : 6 - 6 (1 bit)

TIMER12RST : TIMER12 timer reset
bits : 7 - 7 (1 bit)

TIMER13RST : TIMER13 timer reset
bits : 8 - 8 (1 bit)

WWDGTRST : Window watchdog timer reset
bits : 11 - 11 (1 bit)

SPI1RST : SPI1 reset
bits : 14 - 14 (1 bit)

SPI2RST : SPI2 reset
bits : 15 - 15 (1 bit)

USART1RST : USART1 reset
bits : 17 - 17 (1 bit)

USART2RST : USART2 reset
bits : 18 - 18 (1 bit)

UART3RST : UART3 reset
bits : 19 - 19 (1 bit)

UART4RST : UART4 reset
bits : 20 - 20 (1 bit)

I2C0RST : I2C0 reset
bits : 21 - 21 (1 bit)

I2C1RST : I2C1 reset
bits : 22 - 22 (1 bit)

I2C2RST : I2C2 reset
bits : 23 - 23 (1 bit)

CAN0RST : CAN0 reset
bits : 25 - 25 (1 bit)

CAN1RST : CAN1 reset
bits : 26 - 26 (1 bit)

PMURST : Power control reset
bits : 28 - 28 (1 bit)

DACRST : DAC reset
bits : 29 - 29 (1 bit)

UART6RST : UART6 reset
bits : 30 - 30 (1 bit)

UART7RST : UART7 reset
bits : 31 - 31 (1 bit)

TIMER0RST : TIMER0 reset
bits : 0 - 0 (1 bit)

TIMER7RST : TIMER7 reset
bits : 1 - 1 (1 bit)

USART0RST : USART0 reset
bits : 4 - 4 (1 bit)

USART5RST : USART5 reset
bits : 5 - 5 (1 bit)

ADCRST : ADC reset
bits : 8 - 8 (1 bit)

SDIORST : SDIO reset
bits : 11 - 11 (1 bit)

SPI0RST : SPI0 Reset
bits : 12 - 12 (1 bit)

SPI3RST : SPI3 Reset
bits : 13 - 13 (1 bit)

SYSCFGRST : SYSCFG Reset
bits : 14 - 14 (1 bit)

TIMER8RST : TIMER8 reset
bits : 16 - 16 (1 bit)

TIMER9RST : TIMER9 reset
bits : 17 - 17 (1 bit)

TIMER10RST : TIMER10 reset
bits : 18 - 18 (1 bit)

SPI4RST : SPI4 Reset
bits : 20 - 20 (1 bit)

SPI5RST : SPI5 Reset
bits : 21 - 21 (1 bit)

TLIRST : TLI Reset
bits : 26 - 26 (1 bit)

PAEN : GPIO port A clock enable
bits : 0 - 0 (1 bit)

PBEN : GPIO port B clock enable
bits : 1 - 1 (1 bit)

PCEN : GPIO port C clock enable
bits : 2 - 2 (1 bit)

PDEN : GPIO port D clock enable
bits : 3 - 3 (1 bit)

PEEN : GPIO port E clock enable
bits : 4 - 4 (1 bit)

PFEN : GPIO port F clock enable
bits : 5 - 5 (1 bit)

PGEN : GPIO port G clock enable
bits : 6 - 6 (1 bit)

PHEN : GPIO port H clock enable
bits : 7 - 7 (1 bit)

PIEN : GPIO port I clock enable
bits : 8 - 8 (1 bit)

CRCEN : CRC clock enable
bits : 12 - 12 (1 bit)

BKPSRAMEN : BKPSRAM clock enable
bits : 18 - 18 (1 bit)

TCMSRAMEN : TCMSRAM clock enable
bits : 20 - 20 (1 bit)

DMA0EN : DMA0 clock enable
bits : 21 - 21 (1 bit)

DMA1EN : DMA1 clock enable
bits : 22 - 22 (1 bit)

IPAEN : IPA clock enable
bits : 23 - 23 (1 bit)

ENETEN : Ethernet clock enable
bits : 25 - 25 (1 bit)

ENETTXEN : Ethernet TX clock enable
bits : 26 - 26 (1 bit)

ENETRXEN : Ethernet RX clock enable
bits : 27 - 27 (1 bit)

ENETPTPEN : Ethernet PTP clock enable
bits : 28 - 28 (1 bit)

USBHSEN : USBHS clock enable
bits : 29 - 29 (1 bit)

USBHSULPIEN : USBHS ULPI clock enable
bits : 30 - 30 (1 bit)

DCIEN : DCI clock enable
bits : 0 - 0 (1 bit)

TRNGEN : TRNG clock enable
bits : 6 - 6 (1 bit)

USBFSEN : USBFS clock enable
bits : 7 - 7 (1 bit)

EXMCEN : EXMC clock enable
bits : 0 - 0 (1 bit)

PLLPSC : The PLL VCO source clock prescaler
bits : 0 - 5 (6 bit)
access : read-write

PLLN : The PLL VCO clock multi factor
bits : 6 - 14 (9 bit)
access : read-write

PLLP : The PLLP output frequency division factor from PLL VCO clock
bits : 16 - 17 (2 bit)
access : read-write

PLLSEL : PLL Clock Source Selection
bits : 22 - 22 (1 bit)
access : read-write

PLLQ : The PLL Q output frequency division factor from PLL VCO clock
bits : 24 - 27 (4 bit)
access : read-write

TIMER1EN : TIMER1 timer clock enable
bits : 0 - 0 (1 bit)

TIMER2EN : TIMER2 timer clock enable
bits : 1 - 1 (1 bit)

TIMER3EN : TIMER3 timer clock enable
bits : 2 - 2 (1 bit)

TIMER4EN : TIMER4 timer clock enable
bits : 3 - 3 (1 bit)

TIMER5EN : TIMER5 timer clock enable
bits : 4 - 4 (1 bit)

TIMER6EN : TIMER6 timer clock enable
bits : 5 - 5 (1 bit)

TIMER11EN : TIMER11 timer clock enable
bits : 6 - 6 (1 bit)

TIMER12EN : TIMER12 timer clock enable
bits : 7 - 7 (1 bit)

TIMER13EN : TIMER13 timer clock enable
bits : 8 - 8 (1 bit)

WWDGTEN : Window watchdog timer clock enable
bits : 11 - 11 (1 bit)

SPI1EN : SPI1 clock enable
bits : 14 - 14 (1 bit)

SPI2EN : SPI2 clock enable
bits : 15 - 15 (1 bit)

USART1EN : USART1 clock enable
bits : 17 - 17 (1 bit)

USART2EN : USART2 clock enable
bits : 18 - 18 (1 bit)

UART3EN : UART3 clock enable
bits : 19 - 19 (1 bit)

UART4EN : UART4 clock enable
bits : 20 - 20 (1 bit)

I2C0EN : I2C0 clock enable
bits : 21 - 21 (1 bit)

I2C1EN : I2C1 clock enable
bits : 22 - 22 (1 bit)

I2C2EN : I2C2 clock enable
bits : 23 - 23 (1 bit)

CAN0EN : CAN0 clock enable
bits : 25 - 25 (1 bit)

CAN1EN : CAN1 clock enable
bits : 26 - 26 (1 bit)

PMUEN : Power control clock enable
bits : 28 - 28 (1 bit)

DACEN : DAC clock enable
bits : 29 - 29 (1 bit)

UART6EN : UART6 clock enable
bits : 30 - 30 (1 bit)

UART7EN : UART7 clock enable
bits : 31 - 31 (1 bit)

TIMER0EN : TIMER0 clock enable
bits : 0 - 0 (1 bit)

TIMER7EN : TIMER7 clock enable
bits : 1 - 1 (1 bit)

USART0EN : USART0 clock enable
bits : 4 - 4 (1 bit)

USART5EN : USART5 clock enable
bits : 5 - 5 (1 bit)

ADC0EN : ADC0 clock enable
bits : 8 - 8 (1 bit)

ADC1EN : ADC1 clock enable
bits : 9 - 9 (1 bit)

ADC2EN : ADC2 clock enable
bits : 10 - 10 (1 bit)

SDIOEN : SDIO clock enable
bits : 11 - 11 (1 bit)

SPI0EN : SPI0 clock enable
bits : 12 - 12 (1 bit)

SPI3EN : SPI3 clock enable
bits : 13 - 13 (1 bit)

SYSCFGEN : SYSCFG clock enable
bits : 14 - 14 (1 bit)

TIMER8EN : TIMER8 clock enable
bits : 16 - 16 (1 bit)

TIMER9EN : TIMER9 clock enable
bits : 17 - 17 (1 bit)

TIMER10EN : TIMER10 clock enable
bits : 18 - 18 (1 bit)

SPI4EN : SPI4 clock enable
bits : 20 - 20 (1 bit)

SPI5EN : SPI5 clock enable
bits : 21 - 21 (1 bit)

TLIEN : TLI clock enable
bits : 26 - 26 (1 bit)

PASPEN : GPIO port A clock enable when sleep mode
bits : 0 - 0 (1 bit)

PBSPEN : GPIO port B clock enable when sleep mode
bits : 1 - 1 (1 bit)

PCSPEN : GPIO port C clock enable when sleep mode
bits : 2 - 2 (1 bit)

PDSPEN : GPIO port D clock enable when sleep mode
bits : 3 - 3 (1 bit)

PESPEN : GPIO port E clock enable when sleep mode
bits : 4 - 4 (1 bit)

PFSPEN : GPIO port F clock enable when sleep mode
bits : 5 - 5 (1 bit)

PGSPEN : GPIO port G clock enable when sleep mode
bits : 6 - 6 (1 bit)

PHSPEN : GPIO port H clock enable when sleep mode
bits : 7 - 7 (1 bit)

PISPEN : GPIO port I clock enable when sleep mode
bits : 8 - 8 (1 bit)

CRCSPEN : CRC clock enable when sleep mode
bits : 12 - 12 (1 bit)

FMCSPEN : FMC clock enable when sleep mode
bits : 15 - 15 (1 bit)

SRAM0SPEN : SRAM0 clock enable when sleep mode
bits : 16 - 16 (1 bit)

SRAM1SPEN : SRAM1 clock enable when sleep mode
bits : 17 - 17 (1 bit)

BKPSRAMSPEN : BKPSRAM clock enable when sleep mode
bits : 18 - 18 (1 bit)

SRAM2SPEN : SRAM2 clock enable when sleep mode
bits : 19 - 19 (1 bit)

DMA0SPEN : DMA0 clock enable when sleep mode
bits : 21 - 21 (1 bit)

DMA1SPEN : DMA1 clock enable when sleep mode
bits : 22 - 22 (1 bit)

IPASPEN : IPA clock enable when sleep mode
bits : 23 - 23 (1 bit)

ENETSPEN : Ethernet clock enable when sleep mode
bits : 25 - 25 (1 bit)

ENETTXSPEN : Ethernet TX clock enable when sleep mode
bits : 26 - 26 (1 bit)

ENETRXSPEN : Ethernet RX clock enable when sleep mode
bits : 27 - 27 (1 bit)

ENETPTPSPEN : Ethernet PTP clock enable when sleep mode
bits : 28 - 28 (1 bit)

USBHSSPEN : USBHS clock enable when sleep mode
bits : 29 - 29 (1 bit)

USBHSULPISPEN : USBHS ULPI clock enable when sleep mode
bits : 30 - 30 (1 bit)

DCISPEN : DCI clock enable when sleep mode
bits : 0 - 0 (1 bit)

TRNGSPEN : TRNG clock enable when sleep mode
bits : 6 - 6 (1 bit)

USBFSSPEN : USBFS clock enable when sleep mode
bits : 7 - 7 (1 bit)

EXMCSPEN : EXMC clock enable when sleep mode
bits : 0 - 0 (1 bit)

TIMER1SPEN : TIMER1 timer clock enable when sleep mode
bits : 0 - 0 (1 bit)

TIMER2SPEN : TIMER2 timer clock enable when sleep mode
bits : 1 - 1 (1 bit)

TIMER3SPEN : TIMER3 timer clock enable when sleep mode
bits : 2 - 2 (1 bit)

TIMER4SPEN : TIMER4 timer clock enable when sleep mode
bits : 3 - 3 (1 bit)

TIMER5SPEN : TIMER5 timer clock enable when sleep mode
bits : 4 - 4 (1 bit)

TIMER6SPEN : TIMER6 timer clock enable when sleep mode
bits : 5 - 5 (1 bit)

TIMER11SPEN : TIMER11 timer clock enable when sleep mode
bits : 6 - 6 (1 bit)

TIMER12SPEN : TIMER12 timer clock enable when sleep mode
bits : 7 - 7 (1 bit)

TIMER13SPEN : TIMER13 timer clock enable when sleep mode
bits : 8 - 8 (1 bit)

WWDGTSPEN : Window watchdog timer clock enable when sleep mode
bits : 11 - 11 (1 bit)

SPI1SPEN : SPI1 clock enable when sleep mode
bits : 14 - 14 (1 bit)

SPI2SPEN : SPI2 clock enable when sleep mode
bits : 15 - 15 (1 bit)

USART1SPEN : USART1 clock enable when sleep mode
bits : 17 - 17 (1 bit)

USART2SPEN : USART2 clock enable when sleep mode
bits : 18 - 18 (1 bit)

UART3SPEN : UART3 clock enable when sleep mode
bits : 19 - 19 (1 bit)

UART4SPEN : UART4 clock enable when sleep mode
bits : 20 - 20 (1 bit)

I2C0SPEN : I2C0 clock enable when sleep mode
bits : 21 - 21 (1 bit)

I2C1SPEN : I2C1 clock enable when sleep mode
bits : 22 - 22 (1 bit)

I2C2SPEN : I2C2 clock enable when sleep mode
bits : 23 - 23 (1 bit)

CAN0SPEN : CAN0 clock enable when sleep mode
bits : 25 - 25 (1 bit)

CAN1SPEN : CAN1 clock enable when sleep mode
bits : 26 - 26 (1 bit)

PMUSPEN : Power control clock enable when sleep mode
bits : 28 - 28 (1 bit)

DACSPEN : DAC clock enable when sleep mode
bits : 29 - 29 (1 bit)

UART6SPEN : UART6 clock enable when sleep mode
bits : 30 - 30 (1 bit)

UART7SPEN : UART7 clock enable when sleep mode
bits : 31 - 31 (1 bit)

TIMER0SPEN : TIMER0 clock enable when sleep mode
bits : 0 - 0 (1 bit)

TIMER7SPEN : TIMER7 clock enable when sleep mode
bits : 1 - 1 (1 bit)

USART0SPEN : USART0 clock enable when sleep mode
bits : 4 - 4 (1 bit)

USART5SPEN : USART5 clock enable when sleep mode
bits : 5 - 5 (1 bit)

ADC0SPEN : ADC0 clock enable when sleep mode
bits : 8 - 8 (1 bit)

ADC1SPEN : ADC1 clock enable when sleep mode
bits : 9 - 9 (1 bit)

ADC2SPEN : ADC2 clock enable when sleep mode
bits : 10 - 10 (1 bit)

SDIOSPEN : SDIO clock enable when sleep mode
bits : 11 - 11 (1 bit)

SPI0SPEN : SPI0 clock enable when sleep mode
bits : 12 - 12 (1 bit)

SPI3SPEN : SPI3 clock enable when sleep mode
bits : 13 - 13 (1 bit)

SYSCFGSPEN : SYSCFG clock enable when sleep mode
bits : 14 - 14 (1 bit)

TIMER8SPEN : TIMER8 clock enable when sleep mode
bits : 16 - 16 (1 bit)

TIMER9SPEN : TIMER9 clock enable when sleep mode
bits : 17 - 17 (1 bit)

TIMER10SPEN : TIMER10 clock enable when sleep mode
bits : 18 - 18 (1 bit)

SPI4SPEN : SPI4 clock enable when sleep mode
bits : 20 - 20 (1 bit)

SPI5SPEN : SPI5 clock enable when sleep mode
bits : 21 - 21 (1 bit)

TLISPEN : TLI clock enable when sleep mode
bits : 26 - 26 (1 bit)

LXTALEN : LXTAL enable
bits : 0 - 0 (1 bit)
access : read-write

LXTALSTB : External low-speed oscillator stabilization
bits : 1 - 1 (1 bit)
access : read-only

LXTALBPS : LXTAL bypass mode enable
bits : 2 - 2 (1 bit)
access : read-write

LXTALDRI : LXTAL drive capability
bits : 3 - 4 (2 bit)
access : read-write

RTCSRC : RTC clock entry selection
bits : 8 - 9 (2 bit)
access : read-write

RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)
access : read-write

BKPRST : Backup domain reset
bits : 16 - 16 (1 bit)
access : read-write

IRC32KEN : IRC32K enable
bits : 0 - 0 (1 bit)
access : read-write

IRC32KSTB : IRC32K stabilization
bits : 1 - 1 (1 bit)
access : read-only

RSTFC : Reset flag clear
bits : 24 - 24 (1 bit)
access : read-write

BORRSTF : BOR reset flag
bits : 25 - 25 (1 bit)
access : read-only

EPRSTF : External PIN reset flag
bits : 26 - 26 (1 bit)
access : read-only

PORRSTF : Power reset flag
bits : 27 - 27 (1 bit)
access : read-only

SWRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-only

FWDGTRSTF : Free Watchdog timer reset flag
bits : 29 - 29 (1 bit)
access : read-only

WWDGTRSTF : Window watchdog timer reset flag
bits : 30 - 30 (1 bit)
access : read-only

LPRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
access : read-only

SCS : System clock switch
bits : 0 - 1 (2 bit)
access : read-write

SCSS : System clock switch status
bits : 2 - 3 (2 bit)
access : read-only

AHBPSC : AHB prescaler selection
bits : 4 - 7 (4 bit)
access : read-write

APB1PSC : APB1 prescaler selection
bits : 10 - 12 (3 bit)
access : read-write

APB2PSC : APB2 prescaler selection
bits : 13 - 15 (3 bit)
access : read-write

RTCDIV : RTC clock divider factor
bits : 16 - 20 (5 bit)
access : read-write

CKOUT0SEL : CKOUT0 Clock Source Selection
bits : 21 - 22 (2 bit)
access : read-write

I2SSEL : I2S Clock Source Selection
bits : 23 - 23 (1 bit)
access : read-write

CKOUT0DIV : The CK_OUT0 divider which the CK_OUT0 frequency can be reduced
bits : 24 - 26 (3 bit)
access : read-write

CKOUT1DIV : The CK_OUT1 divider which the CK_OUT1 frequency can be reduced
bits : 27 - 29 (3 bit)
access : read-write

CKOUT1SEL : CKOUT1 Clock Source Selection
bits : 30 - 31 (2 bit)
access : read-write

MODCNT : configure PLL spread spectrum modulation profile amplitude and frequency
bits : 0 - 12 (13 bit)
access : read-write

MODSTEP : configure PLL spread spectrum modulation profile amplitude and frequency
bits : 13 - 27 (15 bit)
access : read-write

SS_TYPE : PLL spread spectrum modulation type select
bits : 30 - 30 (1 bit)
access : read-write

SSCGON : PLL spread spectrum modulation enable
bits : 31 - 31 (1 bit)
access : read-write

PLLI2SPSC : The PLLI2S VCO source clock prescaler
bits : 0 - 5 (6 bit)
access : read-write

PLLI2SN : The PLLI2S VCO clock multi factor
bits : 6 - 14 (9 bit)
access : read-write

PLLI2SQ : The PLLI2S Q output frequency division factor from PLLI2S VCO clock
bits : 24 - 27 (4 bit)
access : read-write

PLLI2SR : The PLLI2S R output frequency division factor from PLLI2S VCO clock
bits : 28 - 30 (3 bit)
access : read-write

PLLSAIN : The PLLSAI VCO clock multi factor
bits : 6 - 14 (9 bit)
access : read-write

PLLSAIP : The PLLSAI P output frequency division factor from PLLSAI VCO clock
bits : 16 - 17 (2 bit)
access : read-write

PLLSAIQ : The PLLI2S Q output frequency division factor from PLLI2S VCO clock
bits : 24 - 27 (4 bit)
access : read-write

PLLSAIR : The PLLSAI R output frequency division factor from PLLSAI VCO clock
bits : 28 - 30 (3 bit)
access : read-write

PLLSAIRDIV : The divider factor from PLLSAIR clock
bits : 16 - 17 (2 bit)

TIMERSEL : TIMER clock selection
bits : 24 - 24 (1 bit)

IRC32KSTBIF : IRC32K stabilization interrupt flag
bits : 0 - 0 (1 bit)
access : read-only

LXTALSTBIF : LXTAL stabilization interrupt flag
bits : 1 - 1 (1 bit)
access : read-only

IRC16MSTBIF : IRC16M stabilization interrupt flag
bits : 2 - 2 (1 bit)
access : read-only

HXTALSTBIF : HXTAL stabilization interrupt flag
bits : 3 - 3 (1 bit)
access : read-only

PLLSTBIF : PLL stabilization interrupt flag
bits : 4 - 4 (1 bit)
access : read-only

PLLI2SSTBIF : PLLI2S stabilization interrupt flag
bits : 5 - 5 (1 bit)
access : read-only

PLLSAISTBIF : PLLSAI stabilization interrupt flag
bits : 6 - 6 (1 bit)
access : read-only

CKMIF : HXTAL Clock Stuck Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-only

IRC32KSTBIE : IRC32K Stabilization interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

LXTALSTBIE : LXTAL Stabilization Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

IRC16MSTBIE : IRC16M Stabilization Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

HXTALSTBIE : HXTAL Stabilization Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

PLLSTBIE : PLL Stabilization Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write

PLLI2SSTBIE : PLLI2S Stabilization Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write

PLLSAISTBIE : PLLSAI Stabilization Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write

IRC32KSTBIC : IRC32K Stabilization Interrupt Clear
bits : 16 - 16 (1 bit)
access : write-only

LXTALSTBIC : LXTAL Stabilization Interrupt Clear
bits : 17 - 17 (1 bit)
access : write-only

IRC16MSTBIC : IRC16M Stabilization Interrupt Clear
bits : 18 - 18 (1 bit)
access : write-only

HXTALSTBIC : HXTAL Stabilization Interrupt Clear
bits : 19 - 19 (1 bit)
access : write-only

PLLSTBIC : PLL stabilization Interrupt Clear
bits : 20 - 20 (1 bit)
access : write-only

PLLI2SSTBIC : PLLI2S stabilization Interrupt Clear
bits : 21 - 21 (1 bit)
access : write-only

PLLSAISTBIC : PLLSAI stabilization Interrupt Clear
bits : 22 - 22 (1 bit)
access : write-only

CKMIC : HXTAL Clock Stuck Interrupt Clear
bits : 23 - 23 (1 bit)
access : write-only

CK48MSEL : 48MHz clock selection
bits : 0 - 0 (1 bit)
access : read-write

PLL48MSEL : PLL48M clock selection
bits : 1 - 1 (1 bit)
access : read-write

IRC48MEN : Internal 48MHz RC oscillator enable
bits : 16 - 16 (1 bit)
access : read-write

IRC48MSTB : Internal 48MHz RC oscillator clock stabilization Flag
bits : 17 - 17 (1 bit)
access : read-only

IRC48MCAL : Internal 48MHz RC oscillator calibration value register
bits : 24 - 31 (8 bit)
access : read-only

IRC48MSTBIF : IRC48M stabilization interrupt flag
bits : 6 - 6 (1 bit)
access : read-only

IRC48MSTBIE : Internal 48 MHz RC oscillator Stabilization Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write

IRC48MSTBIC : Internal 48 MHz RC oscillator Stabilization Interrupt Clear
bits : 22 - 22 (1 bit)
access : write

CTCRST : CTC reset
bits : 27 - 27 (1 bit)
access : read-write

IREFRST : IREF reset
bits : 31 - 31 (1 bit)
access : read-write

CTCEN : CTC clock enable
bits : 27 - 27 (1 bit)
access : read-write

IREFEN : IREF interface clock enable
bits : 31 - 31 (1 bit)
access : read-write

CTCSPEN : CTC enable when sleep mode
bits : 27 - 27 (1 bit)
access : read-write

IREFSPEN : IREF enable when sleep mode
bits : 31 - 31 (1 bit)
access : read-write